Silicon carbide power device chip bonding method

Abstract

The invention discloses a silicon carbide power device chip bonding method, and belongs to the technical field of microelectronic packaging. The bonding method provided by the invention comprises thefollowing steps: providing a blocking layer and a bonding layer in sequence on a passive surface and a substrate panel of a silicon carbide power device wafer; printing nano-silver soldering paste onthe silicon carbide power device wafer and the substrate panel at uniform thickness for performing pressureless sintering to form a silver sintered layer; performing oxidization and polishing treatment on the silver sintered layer; cutting the treated silver sintered layer to form a separate silicon carbide power device chip and a substrate; and placing the silver sintered layer on the silicon carbide power device wafer to the silver sintered layer on the substrate in a surface mounting manner for thermocompression bonding, so that the bonding connection of the silicon carbide power device chip is realized. The silicon carbide power device chip bonding method has the characteristics of easiness, high reliability and high yield.

Description

technical field [0001] The invention relates to microelectronic packaging technology, especially silicon carbide power device chip packaging technology. Background technique [0002] The rapid development of aerospace, electric vehicles and new energy power generation technology has made the performance indicators of power electronic systems increasingly demanding. The development of high-power device chips used in extreme environments such as high temperature is the key direction of the current development of power electronics technology. Since power device chips based on the first-generation semiconductor material silicon (Si) and the second-generation semiconductor material (GaAs) cannot continue to work in a high-temperature environment above 200 ° C, the silicon carbide (SiC) material developed later The limit operating temperature of the third-generation wide bandgap semiconductor device chip represented by it can reach about 500°C or even higher, which can better meet...

AI Technical Summary

Problems solved by technology

During the sintering process, pressure is required to form a relatively dense sintered layer with low porosity, which makes it difficult to accurately control the thickness of the sintered silver layer, and the thickness of the silver sintered layer is limited to a few microns to tens of microns

If the thickness of the sintered silver layer is too thin, excessive shear strain and stress concentration will occur due to the difference in the thermal expansion coefficient (CTE) of the package structure material in a high temperature environment, resulting in a serious decrease in the reliability of the sintered silver layer

At the same time, the silver sintered layer will grow grains and pores under high temperature environment, resulting in coarsening of the microstructure, causing constitutive degradation of the silver sintered layer, and more prone to fatigue failure

In addition, if the size of the bonded chip is too large, the volatilization of the organic solvent in the silver solder paste will be hindered during sintering, and a large area of ​​pore defects will be formed in the sintered layer, resulting in a significant decrease in bonding strength, making it difficult to achieve high-quality and high-yield sintering

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