Method for preparing magnetic tunnel junction unit array

Abstract

The invention discloses a method for preparing a magnetic tunnel junction unit array. The method concretely comprises the steps of: providing a CMOS substrate with a metal connection line Mx (x is notless than 1) with a polished surface; on the CMOS substrate with the metal connection line Mx with the polished surface, manufacturing a BEV (Bottom Electrode Via); manufacturing a bottom electrode contact / bottom electrode on the BEV; depositing a magnetic tunnel junction multilayer film and a top electrode on the flattened bottom electrode, graphically defining a magnetic tunnel junction pattern, etching the top electrode, the magnetic tunnel junction and the bottom electrode metal, and finally depositing an insulating covering layer around the etched magnetic tunnel junction. The method forpreparing the magnetic tunnel junction unit array manufactures a W BEV, a non-Cu bottom electrode contact / bottom electrode, a magnetic tunnel junction and a top electrode on a CMOS metal connecting line with the polished surface, and allows BEV (Bottom Electrode Via), BEC (Bottom Electrode Contact), BE (Bottom Electrode), MTJ (Magnetic Tunnel Junction) and TE (Top Electrode) to be sequentially and upwards overlapped and aligned.

Description

technical field [0001] The invention relates to the technical field of magnetic random access memory (Magnetic Random Access Memory, MRAM), in particular to a method for preparing a magnetic tunnel junction cell array. Background technique [0002] In recent years, MRAM using Magnetic Tunnel Junction (MTJ) is considered to be the future solid-state non-volatile memory, which has the characteristics of high-speed reading and writing, large capacity and low energy consumption. Ferromagnetic MTJ is usually Sandwich structure, in which there is a magnetic memory layer, which can change the magnetization direction to record different data; an insulating tunnel barrier layer in the middle; a magnetic reference layer, which is located on the other side of the tunnel barrier layer, and its magnetization direction remains unchanged . [0003] In order to record information in this magnetoresistive element, it is recommended to use a writing method based on spin-momentum transfer or ...

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Problems solved by technology

[0004] However, when performing chemical mechanical planarization on patterned CMOS via holes, due to the existence of butterfly defects, the surface flatness will not meet the requirements for making magnetic tunnel junctions (MTJ), which will It is very detrimental to the improvement of the magnetic properties, electricity and yield of the magnetic tunnel junction (MTJ). Patent US2018 / 0358070A1 discloses a method for fabricating a magnetic tunnel junction (MTJ). Immediately after fabrication, a layer of bottom electrode (Bottom Electrode, BE) is deposited, and a chemical mechanical polishing (CMP) process is selected to planarize the bottom electrode (BE) to achieve the fabrication of a magnetic tunnel junction (MTJ) multilayer Film requirements, in this scheme, although the size of the BEV is smaller than the size of the MTJ, there is no etch stop layer for MTJ etching, and over etching will inevitably occur , so that there is a high requirement for the height of the W via hole, which not only leads to a high resistance value of the W via hole, but also limits the increase in the density of the MRAM device. With the miniaturization of the MRAM device, there will be alignment of BEV and BE Deviation (such as Figure 11 shown), resulting in an open circuit from the BEV to the MTJ

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