Semiconductor structures and methods of forming them

A technology of semiconductor and protection structure, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of NMOS transistor positive bias temperature instability, PMOS transistor negative bias temperature instability and other problems, to reduce the bias voltage Temperature Instability, Reduced Change, Reduced Effect of Drift
CN110400746BActive Publication Date: 2022-01-11SEMICON MFG INT (SHANGHAI) CORP +1

Patent Information

Authority / Receiving Office
CN ยท China
Patent Type
Patents(China)
Current Assignee / Owner
SEMICON MFG INT (SHANGHAI) CORP
Publication Date
2022-01-11

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Abstract

A semiconductor structure and its forming method, wherein, the forming method includes: providing a substrate; forming a gate dielectric layer on the substrate; performing a ventilation treatment on the gate dielectric layer to form a modified gate dielectric layer; A work function layer is formed on the modified gate dielectric layer; a gate layer is formed on the work function layer. The ventilation treatment can make nitrogen atoms fill the vacancies and gaps in the gate dielectric layer, thereby preventing the metal atoms in the work function layer from diffusing into the gate dielectric layer, thereby reducing the change of the work function of the gate dielectric layer , thereby reducing the drift of the threshold voltage of the formed semiconductor structure, and reducing the instability of the bias voltage of the formed semiconductor structure.
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Description

technical field

[0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique

[0002] As the integration level of semiconductor integrated circuits becomes higher and higher, the requirements for the reliability of transistors are also higher and higher. In a CMOS process, bias temperature instability (BTI) is an important indicator when evaluating the reliability of a PMOS transistor.

[0003] Bias temperature instability refers to the threshold voltage of the device under high temperature stress or high voltage stress, with the increase of time, it drifts to a more positive or negative direction, the subthreshold slope decreases, and the transconductance and leakage current become smaller, etc. , causing a mismatch between transistors in the circuit.

[0004] Bias temperature instability includes positive bias temperature instability and negative bias temp...

Claims

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