Semiconductor structures and methods of forming them

A technology of semiconductor and protection structure, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of NMOS transistor positive bias temperature instability, PMOS transistor negative bias temperature instability and other problems, to reduce the bias voltage Temperature Instability, Reduced Change, Reduced Effect of Drift

Active Publication Date: 2022-01-11
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Especially in the high-k dielectric layer plus metal gate transistor, due to the existence of more charge traps in the high-k dielectric layer, the temperature instability of the positive bias voltage of the NMOS transistor and the instability of the negative bias voltage temperature of the PMOS transistor change. more serious

Method used

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  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them

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Experimental program
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Embodiment Construction

[0034] There are many problems in the method for forming the semiconductor structure, for example, the bias temperature instability of the formed semiconductor structure is serious.

[0035] Combining with a method of forming a semiconductor structure, the reasons for the serious bias temperature instability of the formed semiconductor structure are analyzed:

[0036] Figure 1 to Figure 2 It is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0037] Please refer to figure 1 , providing a substrate 100; forming a gate structure on the substrate 100, the gate structure comprising: a high-k dielectric layer 111 on the substrate 100; the function layer 131 ; the metal gate 121 located on the work function layer 131 .

[0038] Please refer to figure 2 , forming a source-drain doped layer 140 in the substrate 100 on both sides of the gate structure; annealing the source-drain doped layer 140 to activate dopant ions in the source-...

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Abstract

A semiconductor structure and its forming method, wherein, the forming method includes: providing a substrate; forming a gate dielectric layer on the substrate; performing a ventilation treatment on the gate dielectric layer to form a modified gate dielectric layer; A work function layer is formed on the modified gate dielectric layer; a gate layer is formed on the work function layer. The ventilation treatment can make nitrogen atoms fill the vacancies and gaps in the gate dielectric layer, thereby preventing the metal atoms in the work function layer from diffusing into the gate dielectric layer, thereby reducing the change of the work function of the gate dielectric layer , thereby reducing the drift of the threshold voltage of the formed semiconductor structure, and reducing the instability of the bias voltage of the formed semiconductor structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] As the integration level of semiconductor integrated circuits becomes higher and higher, the requirements for the reliability of transistors are also higher and higher. In a CMOS process, bias temperature instability (BTI) is an important indicator when evaluating the reliability of a PMOS transistor. [0003] Bias temperature instability refers to the threshold voltage of the device under high temperature stress or high voltage stress, with the increase of time, it drifts to a more positive or negative direction, the subthreshold slope decreases, and the transconductance and leakage current become smaller, etc. , causing a mismatch between transistors in the circuit. [0004] Bias temperature instability includes positive bias temperature instability and negative bias temp...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L29/423
CPCH01L29/401H01L29/42364
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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