Semiconductor structures and methods of forming them

Abstract

A semiconductor structure and its forming method, wherein, the forming method includes: providing a substrate; forming a gate dielectric layer on the substrate; performing a ventilation treatment on the gate dielectric layer to form a modified gate dielectric layer; A work function layer is formed on the modified gate dielectric layer; a gate layer is formed on the work function layer. The ventilation treatment can make nitrogen atoms fill the vacancies and gaps in the gate dielectric layer, thereby preventing the metal atoms in the work function layer from diffusing into the gate dielectric layer, thereby reducing the change of the work function of the gate dielectric layer , thereby reducing the drift of the threshold voltage of the formed semiconductor structure, and reducing the instability of the bias voltage of the formed semiconductor structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] As the integration level of semiconductor integrated circuits becomes higher and higher, the requirements for the reliability of transistors are also higher and higher. In a CMOS process, bias temperature instability (BTI) is an important indicator when evaluating the reliability of a PMOS transistor. [0003] Bias temperature instability refers to the threshold voltage of the device under high temperature stress or high voltage stress, with the increase of time, it drifts to a more positive or negative direction, the subthreshold slope decreases, and the transconductance and leakage current become smaller, etc. , causing a mismatch between transistors in the circuit. [0004] Bias temperature instability includes positive bias temperature instability and negative bias temp...

AI Technical Summary

Problems solved by technology

Especially in the high-k dielectric layer plus metal gate transistor, due to the existence of more charge traps in the high-k dielectric layer, the temperature instability of the positive bias voltage of the NMOS transistor and the instability of the negative bias voltage temperature of the PMOS transistor change. more serious

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