Method and device for reducing positional deviation between chip embedding and photolithographic pattern
A chip and graphics technology, used in semiconductor/solid-state device testing/measurement, semiconductor devices, electrical components, etc., can solve the problems of inaccurate alignment of chip pin patterns, short circuits, embedded chip errors, etc., to improve packaging technology, Simple process steps
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[0035] Example
[0036] (a) Etching SiO at a high-resistant wristwich silicon having a thickness of 500 μm thick 3 inch 2 The film 201 opens a window, making a good chip tank and electroplated metal formation 203, coating a small amount of conductive silver paste 204 for fixing and conducting, embedding the chip (205, 206), all chips and silicon surfaces are substantially parallel, such as image 3 (a) shown in;
[0037] (b) Use the visible light three-dimensional microscope, captured all embedded chips in 20 times, introduce the picture into the autocad mapping software. After the proportion is reduced, the chip is drawn and its pin, and the chip of each chip slot as a reference and the pins of each chip embedded drawn onto the reticle across the wafer, after drawing a pattern of the upper layer chip vias medium reticle and reticle metal layer wiring and passive devices;
[0038] (c) Apply a photoresist, such as image 3 (b), and use the medium through hole mask photolithography, g...
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