Method and device for reducing positional deviation between chip embedding and photolithographic pattern

A chip and graphics technology, used in semiconductor/solid-state device testing/measurement, semiconductor devices, electrical components, etc., can solve the problems of inaccurate alignment of chip pin patterns, short circuits, embedded chip errors, etc., to improve packaging technology, Simple process steps

Active Publication Date: 2021-08-27

SHANGHAI JIAO TONG UNIV

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AI-Extracted Technical Summary

Problems solved by technology

Considering that the chip itself has a processing error of a few microns, and if the chip cavity is etched by a wet method, the cavity wall has an inclination angle of 54.74°, which makes the chip unable to be effectively fixed, and it is difficult for the embedded chip to be positioned exactly in the chip cavity. The center of the body; if dry etching is used, although the inclination angle is large, it is necessary to leave a certain margin to prevent the chip from being embedded, which will also lead to a certain error compared to the ideal position when the chip is embedded.

If more chips need to be packaged on one wafer at the same time, each chip will have a certain offset in different directions, and finally the error will be amplified. For example, chip 105 is located on the left side of the chip cavity, and chip 106 is located on the right side of the chip cavity. If a unified mask is drawn ac...

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Method used

(3) use measurement data calculation or directly on the measurement picture to trace the mode, draw the reticle of upper layer figure,...

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Abstract

The method and device for reducing the positional deviation between chip embedding and photolithographic patterns of the present invention comprise the following steps: Step 1, embedding a chip on a substrate; Step 2, obtaining measurement data of the chip; Step 3, using the measurement data to draw an upper layer pattern The photolithographic mask layout; step 4, to obtain the upper layer graphics. Compared with the prior art, the present invention has the following beneficial effects: after embedding the chip, use precision observation equipment to measure the size and relative position of the chip and its pins, and then use the measured data or pictures to draw a photoresist mask , to solve the problem of short circuit or open circuit between the chip pin and the photoresist pattern on the upper layer caused by the error of chip embedding; the process steps added by the present invention are simple, and the wafer level heterogeneity is greatly improved. Integrated packaging process.

Application Domain

Semiconductor/solid-state device testing/measurementSolid-state devices +2

Technology Topic

Embedded systemPhotoresist +7

Image

Examples

Experimental program(1)

Example Embodiment

[0035] Example

[0036] (a) Etching SiO at a high-resistant wristwich silicon having a thickness of 500 μm thick 3 inch 2 The film 201 opens a window, making a good chip tank and electroplated metal formation 203, coating a small amount of conductive silver paste 204 for fixing and conducting, embedding the chip (205, 206), all chips and silicon surfaces are substantially parallel, such as image 3 (a) shown in;

[0037] (b) Use the visible light three-dimensional microscope, captured all embedded chips in 20 times, introduce the picture into the autocad mapping software. After the proportion is reduced, the chip is drawn and its pin, and the chip of each chip slot as a reference and the pins of each chip embedded drawn onto the reticle across the wafer, after drawing a pattern of the upper layer chip vias medium reticle and reticle metal layer wiring and passive devices;

[0038] (c) Apply a photoresist, such as image 3 (b), and use the medium through hole mask photolithography, generate a medium layer including a through hole pattern on the chip, since the media layer mask is drawn, so the through hole will be accurately opened in the chip pin. Above, such as image 3 (c) shown in;

[0039] (d) Sputter seed layer Cr / Cu, and use a metal layer mask to develop, and then generate a metal layer containing wiring and passive devices on the dielectric layer by electroplating and decycle, by electroplating and decycle. It is also drawn, so the metal wire and passive device will be accurate with the chip pin, such as image 3 (d) shown.

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Description & Claims & Application Information

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Classification and recommendation of technical efficacy words

The process steps are simple
Optimizing the packaging process

Method and device for reducing positional deviation between chip embedding and photolithographic pattern

AI-Extracted Technical Summary

Problems solved by technology

Method used

Abstract

Image

Examples

Example Embodiment

PUM

Description & Claims & Application Information

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