Method and device for reducing positional deviation between chip embedding and photolithographic pattern

Abstract

The method and device for reducing the positional deviation between chip embedding and photolithographic patterns of the present invention comprise the following steps: Step 1, embedding a chip on a substrate; Step 2, obtaining measurement data of the chip; Step 3, using the measurement data to draw an upper layer pattern The photolithographic mask layout; step 4, to obtain the upper layer graphics. Compared with the prior art, the present invention has the following beneficial effects: after embedding the chip, use precision observation equipment to measure the size and relative position of the chip and its pins, and then use the measured data or pictures to draw a photoresist mask , to solve the problem of short circuit or open circuit between the chip pin and the photoresist pattern on the upper layer caused by the error of chip embedding; the process steps added by the present invention are simple, and the wafer level heterogeneity is greatly improved. Integrated packaging process.

Description

technical field [0001] The invention relates to a wafer-level three-dimensional heterogeneous integration process, in particular to a method and a device for reducing positional deviations between chip embedding and photolithographic patterns. Background technique [0002] The wafer-level three-dimensional heterogeneous integration process directly packages and rewires chips and passive devices on the wafer, which can directly use semiconductor process equipment to integrate hundreds or more chips at one time, greatly improving packaging efficiency , It reduces the cost and is an important way to realize system-level packaging. Wafer-level packaging usually uses embedded packaging to package chips, and the basic structure of packaging is metal-dielectric-metal, such as figure 1 As shown, the SiO is first etched 2 The thin film 101 opens a window, and uses the window as a mask to etch a chip cavity in the silicon-based substrate 102, then electroplates the metal formation 1...

AI Technical Summary

Problems solved by technology

Considering that the chip itself has a processing error of a few microns, and if the chip cavity is etched by a wet method, the cavity wall has an inclination angle of 54.74°, which makes the chip unable to be effectively fixed, and it is difficult for the embedded chip to be positioned exactly in the chip cavity. The center of the body; if dry etching is used, although the inclination angle is large, it is necessary to leave a certain margin to prevent the chip from being embedded, which will also lead to a certain error compared to the ideal position when the chip is embedded.

If more chips need to be packaged on one wafer at the same time, each chip will have a certain offset in different directions, and finally the error will be amplified. For example, chip 105 is located on the left side of the chip cavity, and chip 106 is located on the right side of the chip cavity. If a unified mask is drawn according to the traditional process, and then the chip is embedded and the subsequent glue coating, photolithography, and development are carried out, it will cause some chip pins to be unable to be accurately aligned with the through holes on the top, and even misalignment may occur. The upper pattern causes an open circuit or touches the wrong pattern to cause a short circuit

For example, the pins 107 and 108 of the chip 105, and the pins 109 and 110 of the chip 106 have a certain degree of offset from the through holes of the dielectric layer 111 and the wiring on the metal layer 112. If the offset is accumulated If the chip pins are large and the pins are very close together, it may cause the original vias and traces on the pin 108 to not touch the pin 108 at all, resulting in an open circuit; or the vias and traces originally located on the pin 112 and the pin 111 contacts, causing a short circuit

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