Hardware accelerator applied to binarized convolutional neural network and data processing method thereof

Abstract

The invention discloses a hardware accelerator applied to a binarized convolutional neural network and a data processing method of the hardware accelerator. The hardware accelerator comprises a neuralnetwork parameter storage module, a matrix generator module, a convolution calculation array module, a pooling layer module and a global control module. A binary grayscale picture and neural networktraining parameters of each layer are pre-stored in the neural network parameter storage module; the matrix generator is responsible for preparing input data of convolution operation; the convolutioncalculation array is responsible for convolution calculation of a convolution layer; the pooling layer module is responsible for performing pooling operation on the output of the convolution layer; the global control module is responsible for controlling the whole system to work normally. The hardware accelerator aims to improve the operation speed of the convolutional neural network, reduce resources and computing resources consumed by network deployment on a hardware platform, and reduce the power consumption of network operation at the same time.

Description

technical field [0001] The invention belongs to the field of artificial intelligence hardware design, and in particular relates to an accelerator applied to a binary convolutional neural network and a data processing method thereof. Background technique [0002] Convolutional neural networks are derived from artificial neural networks. As a multi-layer perceptual network, it has strong adaptability to various image transformation forms such as image rotation, scaling down or enlargement, and image translation, and can quickly extract image features. It adopts the weight sharing network structure, which has a strong similarity with the biological neural network structure. This structure reduces the number of weights, thereby reducing the complexity of the network model. When inputting multidimensional images to the network, such The advantages of the algorithm are more obvious, so that the image can be directly used as the input of the network, avoiding the complex feature e...

AI Technical Summary

Problems solved by technology

However, among the many technologies they adopt, the feature map input to the first layer still uses full-precision data, and a special computing unit needs to be designed for the first layer calculation, which has poor versatility, high resource consumption and large power loss; traditional Convolution adopts the strategy of multiply-accumulate and popcount algorithm, which does not make maximum use of FPGA internal resources, and the calculation cycle increases; at the same time, the strategy of convolution calculation edge complement +1 or -1 is adopted, the edge data still needs to be calculated, and the amount of calculation increases accordingly , leading to greater consumption of hardware resources and increased computing cycles

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