GaN-based lateral super junction device and manufacturing method thereof

A technology of superjunction device and fabrication method, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems that GaAs power devices cannot meet technological development, narrow band gap, and low breakdown electric field, etc. Small on-resistance, high breakdown voltage and good repeatability

Pending Publication Date: 2020-04-07
SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI
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AI-Extracted Technical Summary

Problems solved by technology

Although the first generation of Si semiconductor power devices has achieved remarkable results, its performance is currently close to the theoretical limit of the material. In addition, with the increasing requirements for frequency and power, the second generation of GaAs semiconductor materials due to their narrow bandgap , low breakdown electric field and other factors, resulti...
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Method used

The device structure that the present invention proposes adopts GaN material to prepare, because its superior characteristic of GaN material, breakdown field intensity can reach 3.3MV/cm, the breakdown voltage of the lateral superjunction device of preparation can improve greatly, close to material theoretical value. In addition, this device contains a P-type GaN (or other P-type material layer) material layer. When a forward voltage is applied to the gate, holes in the P-type material will be injected into the heterojunction, and an equal amount of holes will be injected into the he...
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Abstract

The invention discloses a GaN-based lateral super junction device and a manufacturing method thereof. The lateral super-junction device comprises a heterojunction, a source electrode, a drain electrode and a grid electrode whic are matched with the heterojunction, the heterojunction comprises a first semiconductor and a second semiconductor, the second semiconductor is formed on the first semiconductor, two-dimensional electron gas is formed in the heterojunction, and the source electrode and the drain electrode are electrically connected through the two-dimensional electron gas. The GaN-basedlateral super junction device further comprises a plurality of P-type semiconductors arranged at intervals, and the P-type semiconductors are distributed below the grid electrode. The P-type semiconductors are formed on the first semiconductor, and the source electrode or the drain electrode is connected or not connected with the P-type semiconductors, or the P-type semiconductors are formed on the second semiconductor, and a high-resistance semiconductor is further formed between every two adjacent P-type semiconductors and between the P-type semiconductors and any one of the source electrode and the drain electrode. The GaN-based lateral super junction device provided by the invention is high in breakdown voltage and small in specific on-resistance; and moreover, the manufacturing process is simple and the repeatability is good.

Application Domain

Semiconductor/solid-state device manufacturingSemiconductor devices

Technology Topic

EngineeringElectrical connection +6

Image

  • GaN-based lateral super junction device and manufacturing method thereof
  • GaN-based lateral super junction device and manufacturing method thereof
  • GaN-based lateral super junction device and manufacturing method thereof

Examples

  • Experimental program(4)

Example Embodiment

[0130] Example 1
[0131] See Figure 2a , Figure 2b , A GaN-based lateral superjunction device, which includes a substrate 1, a buffer layer 2 arranged on the substrate 1, a heterojunction arranged on the buffer layer 2, the heterojunction comprising a first semiconductor 3 and a second semiconductor 4. The second semiconductor 4 is formed on the first semiconductor 3, and a two-dimensional electron gas is formed between the first semiconductor and the second semiconductor; the source 7 drain 8 and the gate 9 are arranged on the heterojunction, The source 7 and the drain 8 are all arranged on the second semiconductor 4, and the source and the drain are electrically connected by the two-dimensional electron gas. The second semiconductor 4 is also arranged with a plurality of P-type semiconductors 5 oriented The two ends of the P-type semiconductor 5 point to the source 7 and the drain 8 respectively, between two adjacent P-type semiconductors 5 and between the P-type semiconductor 5 and the source 7 or the drain 8 A high-resistance semiconductor 6 is also formed between any one of them, the gate 9 is arranged above the P-type semiconductor array, and the P-type semiconductor 5 and the high-resistance semiconductor 6 are integrally arranged.

Example Embodiment

[0132] Example 2
[0133] The manufacturing process of a GaN-based lateral super junction device may include the following steps:
[0134] 1) Use metal organic chemical vapor deposition (MOCVD) method to grow as image 3 In the material structure shown, the substrate is Si with a thickness of 400 μm, and the buffer layer is high-resistance GaN with a thickness of 4.2 μm; the thickness of GaN in the AlGaN/GaN heterostructure is 260 nm, the thickness of AlGaN is 18 nm, and the content of Al is 18 %; P-GaN materials are used for P-type semiconductors, and the thickness of P-GaN is 70nm;
[0135] 2) Use inductively coupled plasma to etch the P-GaN layer in the ohmic region, and then use electron beam evaporation technology to deposit Ti/Al/Ni/Au four-layer metal and place it in N 2 Annealed at 875℃ for 30s, the resulting material structure is as Figure 4 Shown
[0136] 3) Treat part of P-GaN with hydrogen plasma to form high resistance GaN (HG-GaN). The processed material structure is as follows Figure 5a , Figure 5b Shown
[0137] 4) Using electron beam evaporation technology to deposit Ni/Au double-layer metal as the gate electrode metal to form a GaN-based lateral superjunction device structure such as Figure 6a , Figure 6b Shown.

Example Embodiment

[0138] Example 3
[0139] See Figure 7a , Figure 7b , A GaN-based lateral superjunction device, which includes a substrate 1, a buffer layer 2 arranged on the substrate 1, a heterojunction arranged on the buffer layer 2, the heterojunction comprising a first semiconductor 3 and a second semiconductor 4. The second semiconductor 4 is formed on the first semiconductor 3, and a two-dimensional electron gas is formed between the first semiconductor and the second semiconductor; the source 7 drain 8 and the gate 9 are arranged on the heterojunction, The source and drain are electrically connected by the two-dimensional electron gas, and a P-type semiconductor array formed by oriented arrangement of a plurality of P-type semiconductors 5 is also arranged on the first semiconductor 3. The ends point to the source 7 and the drain 8 respectively. The source 7 and the drain 8 are both connected to the second semiconductor 4, the gate 9 is located between the source 7 and the drain 8, and the gate 9 is connected to the P-type semiconductor 5 . The second semiconductor 4 and the P-type semiconductor 5 are integrally arranged, and the P-type semiconductor 5 is arranged in the second semiconductor 4.

PUM

PropertyMeasurementUnit
Thickness10.0nm
Thickness100.0nm
Thickness100.0µm

Description & Claims & Application Information

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