multi-die FPGA for realizing clock tree by using active silicon connection layer

Abstract

The invention discloses a multi-die FPGA for realizing a clock tree by using an active silicon connection layer. The multi-die FPGA comprises a plurality of FPGA dies, the plurality of FPGA dies are stacked on the same silicon connection layer, and interconnection communication is realized through cross-die connection lines in the silicon connection layer; active devices are also arranged in the silicon connection layer to construct a balance clock tree; a clock signal is pushed to each FPGA die through the balance clock tree; according to the multi-die FPGA and the manufacturing method thereof, the balance clock tree in the silicon connection layer can balance the time delay of the clock signal reaching each FPGA die, the problem that the clock skew is too large during cross-die communication is reduced, and the design convergence is accelerated, so that the performance of the multi-die FPGA is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a multi-die FPGA that utilizes an active silicon connection layer to realize a clock tree. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) is a hardware programmable logic device. It is not only used in mobile communication, data center and other fields, but also widely used in prototype verification in integrated circuit design, which can effectively verify The correctness of circuit function, while speeding up circuit design. Prototype verification needs to use the programmable logic resources inside FPGA to realize circuit design. With the continuous increase of the scale of integrated circuits and the realization of complex functions, the demand for the number of programmable logic resources of FPGA is constantly increasing. With the continuous increase, the number of FPGA programmable resources will become a gre...

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Problems solved by technology

However, the above two patents are limited by the defects of the chip itself and the structural design. Both of them can only interconnect two adjacent IC dies arranged side by side, and can only realize signal interconnection in a single direction. Very limited

In addition, the balance of cross-die clock signals in this multi-die structure is also a problem that has to be considered, and it is also a big challenge. The conventional approach may be to connect the clock inputs between the die in series, but this It will cause the clock to be out of sync, and the clock skew will be very large, which will seriously affect the performance of cross-die design

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