Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Preparation method of TSV passive adapter plate for three-dimensional system-in-package

A system-level packaging and adapter board technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of silicon material waste and inability to recycle, and achieve cost-saving effects

Active Publication Date: 2020-11-06
FUDAN UNIV +1
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for the thinning of silicon wafers, mechanical grinding is usually used, in which a considerable thickness of silicon material will be removed but cannot be recycled, resulting in a large waste of silicon material

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Preparation method of TSV passive adapter plate for three-dimensional system-in-package
  • Preparation method of TSV passive adapter plate for three-dimensional system-in-package
  • Preparation method of TSV passive adapter plate for three-dimensional system-in-package

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0017] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific The examples are only used to explain the present invention, not to limit the present invention. The described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0018] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical" and "horizontal" are based on the orientation or positional relation...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a preparation method of a TSV passive adapter plate for three-dimensional system-in-package. Low-energy ions are injected into a monocrystalline silicon substrate to a shallowdepth by adopting an ion injection process, and then high-temperature annealing is carried out to form a layer of silicon compound in the silicon substrate, so that the silicon substrate is divided into top silicon at the upper part and bulk silicon at the lower part by the silicon compound. Monocrystalline silicon with a certain thickness is grown on the surface of the top silicon by adopting a molecular beam epitaxy method to serve as a substrate; according to the invention, the silicon material can be fully utilized, the cost is reduced, and the high-density packaging of the chip is realized.

Description

technical field [0001] The invention relates to the field of integrated circuit packaging, in particular to a method for preparing a TSV passive adapter board for three-dimensional system-level packaging. Background technique [0002] With the rapid development of integrated circuit technology, microelectronic packaging technology has gradually become the main factor restricting the development of semiconductor technology. In order to realize the high density of electronic packaging, obtain better performance and lower overall cost, technicians have developed a series of advanced packaging technologies. Among them, the three-dimensional system-in-package technology has good electrical performance and high reliability, and can achieve high packaging density at the same time, and is widely used in various high-speed circuits and miniaturized systems. Through Silicon Via (TSV) interposer technology is a new technology for interconnection of stacked chips in three-dimensional i...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L21/265H01L21/02H01L23/48
CPCH01L21/76898H01L23/481H01L21/26506H01L21/02532H01L21/02631H01L2224/14181
Inventor 朱宝陈琳孙清清张卫
Owner FUDAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com