Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A high-power vcsel array chip flip-chip packaging structure and preparation method

A flip-chip packaging and array chip technology, used in laser parts, semiconductor lasers, electrical components, etc., can solve the problems of restricting the development and application of high-power VCSEL arrays, unstable work efficiency, and poor heat dissipation effect. Material utilization and production efficiency, time saving, thermal stress reduction effect

Active Publication Date: 2021-09-07
BEIJING UNIV OF TECH
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The VCSEL array chip improves the problem of poor beam quality of semiconductor lasers, but because the light-emitting unit of the traditional front-mounted VCSEL array chip packaging process is located on the top of the substrate layer, it cannot be in direct contact with the heat sink, and the heat dissipation effect is poor, resulting in unstable work efficiency. Limits the development and application of high-power VCSEL arrays

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A high-power vcsel array chip flip-chip packaging structure and preparation method
  • A high-power vcsel array chip flip-chip packaging structure and preparation method
  • A high-power vcsel array chip flip-chip packaging structure and preparation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0033] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description. ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
reflectanceaaaaaaaaaa
Login to View More

Abstract

The invention discloses a high-power VCSEL array chip flip-chip packaging structure and a preparation method, comprising: a bottom emission two-dimensional periodic VCSEL array chip, a heat sink and a multi-layer single crystal reflection film layer; a bottom emission two-dimensional periodic VCSEL The array chip includes a substrate layer and a two-dimensional periodic VCSEL light-emitting unit arranged at the bottom of the substrate layer; the bottom of the VCSEL light-emitting unit is connected to the heat sink through a solder layer, and the top of the substrate layer is provided with a multi-layer single crystal reflective film layer; wherein, the thermal The thermal expansion coefficient of the sink is equivalent to that of the substrate layer, and the single crystal reflective film layer has the same lattice structure as the substrate layer. The thermal expansion coefficient of the heat sink of the present invention is equivalent to the thermal expansion coefficient of the substrate layer of the VCSEL array chip, which can reduce the internal thermal stress of the chip and inhibit the deformation of the chip when heated; prepare a multi-layer monolayer on the top of the substrate layer that matches the lattice of the substrate layer. The crystal film layer improves the adhesion between the single crystal reflective layer and the substrate layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor laser chips, in particular to a high-power VCSEL array chip flip-chip packaging structure and a preparation method. Background technique [0002] Compared with edge-emitting semiconductor lasers, vertical cavity surface-emitting lasers (VCSEL) have superior performance such as small size, circular spot, low threshold current, single longitudinal mode output, high coupling efficiency, and easy two-dimensional array integration. Power VCSELs are widely used in laser printing, laser medical treatment, chip lithography, welding processing and other fields. [0003] The VCSEL array chip improves the problem of poor beam quality of semiconductor lasers, but because the light-emitting unit of the traditional front-mounted VCSEL array chip packaging process is located on the top of the substrate layer, it cannot be in direct contact with the heat sink, and the heat dissipation effect is poor, result...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01S5/024H01S5/028H01S5/42
CPCH01S5/02469H01S5/02476H01S5/028H01S5/423
Inventor 王智勇李尉代京京兰天
Owner BEIJING UNIV OF TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products