A fpga-based zuc encryption system ip core construction method

A construction method and encryption system technology, which is applied in the field of FPGA-based ZUC encryption system IP core construction, can solve the problems of leaving traces, reducing security and confidentiality performance, and being easy to be cracked, so as to resist exhaustive attacks and improve confidentiality The effect of performance and convenience

Active Publication Date: 2022-06-07
HEILONGJIANG UNIV
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

From a security point of view, software encryption is easier to crack than hardware encryption, and its encryption process will leave traces on the computer, etc.
Due to speed limitations, software encryption is not suitable for real-time encryption of large amounts of data, such as video communication, video surveillance, etc.
At present, most encryption schemes do not change the key for a long time or manually change the key, resulting in a decrease in its security and confidentiality performance

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A fpga-based zuc encryption system ip core construction method
  • A fpga-based zuc encryption system ip core construction method
  • A fpga-based zuc encryption system ip core construction method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] An IP core construction method for an FPGA-based ZUC and chaotic encryption system, the steps are as follows:

[0039] Step 1: The FPGA adopts the flow management mode, defines the top-level design, and determines the function of each module, as shown in the top-level signal list in Table 1;

[0040] Table 1 Top-level signal list

[0041]

[0042] Step 2: Build an interface module, use the receiving FIFO memory and the transmitting FIFO memory to complete the control and conversion of the three-state gate, and receive data from the outside: including the key KEY and the data to be processed, and send the processed data; such as Figure 5 As shown, the module mainly has a phase-locked loop to generate the clock required by the system, the asynchronous reset and synchronous release module generates a global synchronous reset signal, and the function module collects the falling edge of the external signal to synchronize to the clock domain of the system. FIFO memory wr...

Embodiment 2

[0047] The working process of the encryption system is as follows. First, the key key is input externally, and the key flag signal is given. When the interface module detects that the key flag signal is high, it will send the received data to the key module, and the module will generate 1Mbit key stream, when the interface module detects that the data flag signal is high, it will send the received signal to the data module. When the encryption module detects the data completion signal, it means that the data transmission is completed, and the module will send the key to the key stream at the same time. The module and the data module send a read request signal, and the data and key enter the encryption module for encryption at the same time. At this time, the encryption module pulls the busy signal high, indicating that the FPGA is encrypting, and then writes the encrypted data to the data module and saves it. When all data encryption is completed, the busy signal will be pulled...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides a method for constructing an IP core of an FPGA-based ZUC encryption system. ZUC is used as a key stream generation algorithm, and the output of an improved one-dimensional discrete chaotic system based on the Logistic chaotic system is used as the initial vector IV of ZUC, which is implemented in hardware. When encrypting the system, the flow management mode is used to realize the data interaction between various modules. In this transmission mode, both the upstream and downstream have the right to stop the other party and the obligation to respond to the other party being stopped. The transmission guarantees the correctness of the handshake logic and the continuity of the data. The FIFO memory is added to the corresponding module to cache, so that the upstream and downstream The latent period of inter-divergence can be converged to 1, so that the advantages of FPGA parallel work can be truly utilized, and the running speed of the entire encryption system can be effectively improved. The present invention combines the sequence cipher with chaos through the important parameter initial vector IV in the sequence cipher, so that the key of the whole system can be replaced regularly, thereby further improving the security performance of the whole system.

Description

technical field [0001] The invention belongs to the field of data encryption, in particular to a method for constructing an IP core of an FPGA-based ZUC encryption system. Background technique [0002] ZUC encryption algorithm is a commercial-oriented stream encryption algorithm independently designed by my country. It has been approved as an international standard for a new generation of broadband wireless mobile communication systems. It is a word-oriented stream encryption algorithm. The key KEY and the 128-bit initial vector IV are used as input, and the output of the algorithm is a word sequence with a bit width of 32-bit, that is, the key sequence, which can be used to encrypt and decrypt digital information. [0003] The ZUC encryption algorithm can be logically divided into three layers, from top to bottom, the linear feedback shift register layer (LFSR), the bit reorganization layer (BR) and the nonlinear function layer (F). The basic structure is as follows figure ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): H04L9/00H04L9/08
CPCH04L9/001H04L9/0861Y02D30/50
Inventor 丁群余龙飞李孝友张仁秀丁威
Owner HEILONGJIANG UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap