Transverse SCR anti-static structure for SOI process and preparation method thereof

Abstract

The invention discloses a transverse SCR anti-static structure for an SOI process and a preparation method thereof, and belongs to the technical field of integrated circuits. The SCR anti-static structure integrally adopts an annular structure, comprises four areas, forms a transverse PNPN structure of the SCR, is led out through metal wiring, can adjust impurity concentration and size according to requirements, adopts deep groove isolation, and can be placed at any position of a circuit. High-energy ion implantation and laser annealing are adopted to achieve accurate control over the doping concentration and the size of a doped region, ion implantation is conducted in two steps, the implantation ranges are 40% and 30% of the thickness of an epitaxial layer respectively, impurity re-diffusion is achieved through a laser annealing process, the process is conducted after other structures of the circuit are formed, a thermal process is not needed, and the function and the performance of the circuit are not influenced; and physical and electrical isolation of the SCR anti-static structure is realized by adopting a deep trench isolation process.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a lateral SCR antistatic structure used in SOI technology and a preparation method thereof. Background technique [0002] With the continuous development of integrated circuits, the static electricity generated in the testing, packaging, transportation and other links of integrated circuit chips is the main factor leading to the decline of product reliability. How to design and prepare the antistatic structure of the chip, that is, to meet the antistatic index requirements, At the same time, it is relatively easy to realize, and has become a key topic of research at home and abroad. At present, the more common antistatic structures include diodes, triodes, MOS devices, SCR (silicon controlled silicon), etc., among which the SCR structure is widely used in integrated circuits such as CMOS due to its higher robustness. [0003] With the development of processing techno...

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Problems solved by technology

[0003] With the development of processing technology and the improvement of processing capacity, the size of integrated circuits continues to shrink, and the current mainstream process technology has reached the level of 28nm. Due to the inherent PNPN structure of the SCR structure, the lateral diffusion of impurities, etc., such as figure 1 As shown, the area prepared by the conventional process is relatively large. The traditional SCR structure is mainly formed with the well region or the implanted region, and the doping concentration and the size of the doping region cannot be freely selected, which cannot meet the increasingly high miniaturization requirements. At the same time, too many The impurity implantation and thermal process also have a great impact on the performance of SCR

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