Surface plasmon enhanced LED and preparation method thereof
A surface plasmon, enhanced technology, applied in electrical components, nanotechnology, nanotechnology for information processing, etc., can solve problems such as metal pollution, and achieve the effect of enhancing modulation bandwidth and improving quantum efficiency
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Embodiment 1
[0054] This embodiment provides a surface plasmon enhanced LED, such as Figure 4 As shown, the surface plasmon enhanced LED includes a conductive substrate 109, a metal bonding layer 108, a second insulating layer 107, a DBR reflective layer 105, a p-type GaN layer 104, and an InGaN layer distributed sequentially from bottom to top. / GaN multi-quantum well layer 103, n-type GaN layer 102;
[0055] The surface plasmon enhanced LED also includes a metal P electrode 112, a first insulating layer 111, and a columnar N electrode 106; the metal P electrode 112 runs through the conductive substrate 109, the metal bonding layer 108, and the second Insulating layer 107, DBR reflective layer 105, until the end of the metal P electrode extends to the inside of the p-type GaN layer 104; one end of the metal P electrode extending to the inside of the p-type GaN layer is provided with a metal nanolayer 110; the first insulating Layer 111 is located on the surface of the metal P electrode,...
Embodiment 2
[0077] This embodiment provides an LED chip (LED-2). The difference from Embodiment 1 is mainly reflected in the manufacturing process of the columnar N electrode. After the first wafer is bonded to the second wafer, the columnar electrode hole of the N electrode is made by photolithography and other processes, and then the insulating layer is grown inside the N electrode hole by PECVD, and the top is left during the growth process. A section of the inner wall is not covered by SiO 2 Covering to ensure that the columnar N electrode is connected to the conductive substrate to form electrical conduction, and finally the N electrode is deposited in the columnar hole by a metal evaporation process.
[0078] The concrete difference with embodiment 1 is steps (2)~(5):
[0079](2) Prepare a second insulating layer on the DBR reflective layer; deposit a metal bonding layer on the second insulating layer to obtain a wafer; take another conductive substrate and deposit a metal bonding ...
Embodiment 3
[0089] This embodiment provides an LED chip (LED-3). The difference from Embodiment 1 is mainly reflected in that the bottom of the P electrode channel is a trapezoidal structure or a tooth shape, which can change the etching depth of p-type GaN and the metal nanometer. The coupling distance between the structure and the multi-quantum respect has an impact on the optoelectronic performance. Other structural methods are completely consistent with embodiment 1.
[0090] Figure 8 A cross-sectional view of the surface plasmon-enhanced LED provided for Example 3.
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Abstract
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