Insulated gate type semiconductor device and manufacturing method thereof

Abstract

The initial layer of an epitaxial layer is formed in a n + On the type semiconductor substrate, the crystal plane of one of the substrate surfaces is the (100) plane, and the crystal plane of its orientation plane is the {100} plane. Then, a silicon oxide film is formed on the surface of the initial layer by thermal oxidation, and a nitride film is formed on the silicon oxide film by a CVD process, and then selectively dry-etched to form an n layer having an initial groove. - type epitaxial layer. Next, using the nitride film as a mask, the inner surface of the groove is oxidized, and if the oxide film is formed, the initial groove becomes a U-shaped groove. By optimizing the shape and crystal plane of the U-shaped groove, the electronic performance defect can be reduced and the on-resistance can be reduced.

Description

technical field [0001] The invention relates to an insulating gate type semiconductor device and a manufacturing method thereof. Background technique [0002] figure 1 A conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with U-shaped grooves is shown. exist figure 1 , reference numeral 1 denotes a semiconductor device, which includes a n + type semiconductor substrate 2, and an epitaxial layer 4 located on the semiconductor substrate 2, and a plurality of U-shaped grooves 3 are formed on its surface (only one of them is shown in the figure). The epitaxial layer 4 includes n as the initial layer of the epitaxial layer 4 - type drain region 5, a p located on the drain region 5 - type base region 6, and an n on the surface layer of the base region 6 + Type source region 7. The groove 3 is formed so that it reaches the drain region 5 from the surface of the source region 7 through the base region 6, and the crystal plane of the side wall surface of t...

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Problems solved by technology

[0008] Meanwhile, in the above-mentioned manufacturing method, as the first typical condition for determining the U-shaped groove, if the production conditions selected in the first step are the thickness of the silicon oxide film 12 = 100 Å, the thickness of the silicon nitride film 11 = 1500 Å, and the depth of the groove 14 = 1.5 μm, and the formation temperature of the LOCOS oxide film 15 is selected in the second step = 1000 ° C, although figure 1 The shoulder 3a shown in has an angle, but it has a radius of curvature R of 0.1 μm or less, then when the LOCOS oxide film 15 is formed, displacement occurs in the shoulder 3a due to lattice defects, and in the drain region Leakage current is easily generated under the reverse withstand voltage between 5 and base region 6

In addition, since the concentrated electric field of the gate applies a voltage to the groove shoulder 3a, the gate oxide film 8 is easily damaged, and the gate short circuit phenomenon is easy to occur.

[0009] In addition, as the second typical condition, if the production conditions are such that the thickness of the silicon oxide film 12=100 Å, the thickness of the silicon nitride film 13=500 Å, and the depth of the groove 14=1.5 μm are selected in the first step, and In the second step, the formation temperature of the LOCOS oxide film 15 is selected to be 1100° C. figure 1 If the curvature radius R of the groove shoulder 3a shown in 1 μm is changed to 1 μm, the current leakage or gate short-circuit phenomenon under withstand voltage due to the small curvature radius R is less likely to occur, but due to the silicon nitride film 13 The thickness is relatively thin, and due to the deformation of the groove 3 due to the unfavorable situation that the silicon nitride film 13 is damaged or oxygen passes through the silicon nitride film 13 during the process, the defects of leakage and short circuit are prone to occur

If the radius of curvature R of the groove shoulder 3a is too large, the length of the channel formed in the direction of the semiconductor surface becomes large, which is disadvantageous for on-resistance

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