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LDMOS device and process method

A process method and device technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., to achieve the effect of improving performance and improving the level of electric field optimization

Pending Publication Date: 2021-06-04
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The above-mentioned existing LDMOS structure uses STI in the CMOS process as the field plate dielectric layer of the LDMOS device. Since the STI process is shared with the CMOS device, the parameters of the STI process cannot be changed arbitrarily to optimize the LDMOS device.

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  • LDMOS device and process method
  • LDMOS device and process method
  • LDMOS device and process method

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Embodiment Construction

[0041] The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0042] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientati...

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Abstract

The invention discloses an LDMOS device. A field plate dielectric layer STI, close to one side of a channel, of the LDMOS device is etched and filled with a conductive second doped polycrystalline silicon layer, so that the thickness of the field plate dielectric layer close to a channel region is smaller than the overall thickness of the STI dielectric layer, and the filled polycrystalline silicon layer is in short circuit with a gate polycrystalline silicon layer of the device. The field plate dielectric layer of the device is segmented by the second polycrystalline silicon layer, so that the thickness of the field plate dielectric layer on the side wall of the side, close to the channel, of the second polycrystalline silicon and the thickness of the field plate dielectric layer at the bottom are smaller than the overall thickness of the STI, and the characteristics of the device are further improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an LDMOS device integrated in a BCD process. The invention also relates to the process method of the LDMOS device. Background technique [0002] DMOS (Double-diffused MOS) is currently widely used in power management chips due to its characteristics of high voltage resistance, high current drive capability and extremely low power consumption. In LDMOS (Lateral Double-diffused MOSFET, lateral double-diffused field effect transistor) devices, on-resistance is an important indicator. In the BCD (Bipolar-CMOS-DMOS) process, although LDMOS is integrated with CMOS in the same chip, due to the high breakdown voltage BV (BreakdownVoltage) and low characteristic on-resistance R SP There are contradictions / compromises between (Specific on-Resistance), which often cannot meet the requirements of switching tube applications. High-voltage LDMOS not only has the...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/10H01L29/06H01L21/336
CPCH01L29/66681H01L29/7816H01L29/063H01L29/1033
Inventor 许昭昭
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP