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Semiconductor packaging structure

A packaging structure, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electrical solid-state devices, etc., can solve problems such as DRAM electrostatic damage

Active Publication Date: 2021-07-09
CHANGXIN MEMORY TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is how to prevent the DRAM of BGA package from being damaged by static electricity

Method used

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  • Semiconductor packaging structure
  • Semiconductor packaging structure
  • Semiconductor packaging structure

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Embodiment Construction

[0024] As mentioned in the background art, the DRAM packaged in a ball grid array (BGA, Ball Grid Array) usually causes electrostatic damage.

[0025] Research has found that the current specific process of packaging DRAM in the form of a ball grid array (BGA, Ball Grid Array) includes: forming an integrated circuit corresponding to the DRAM memory on a semiconductor substrate and forming a number of circuits connected to the integrated circuit. Welding pads; forming several pins connected to the several pads, the pins may be solder balls; forming a plastic sealing layer for plastic sealing the integrated circuit, and the plastic sealing layer exposes part of the surface of the pins. In order to ensure that the stress of the packaging structure is uniform during packaging, when forming normal pins connected to the pads, it is also necessary to form a number of floating dummy pins as required (the dummy pins are not in contact with the formed integrated circuit and soldering pad...

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Abstract

A semiconductor packaging structure comprises a semiconductor chip, an electrostatic protection circuit is arranged in the semiconductor chip, a plurality of normal bonding pads and pseudo bonding pads are arranged on the semiconductor chip, and the pseudo bonding pads are connected with the electrostatic protection circuit; the plastic packaging layer is used for plastic packaging of the semiconductor chip, a plurality of normal pins and a plurality of dummy pins are packaged in the plastic packaging layer, the normal pins are connected with the normal bonding pads, and the dummy pins are connected with the dummy bonding pads. When pin array packaging is carried out on a semiconductor chip, the pseudo bonding pad can be connected with an electrostatic protection circuit (an electrostatic protection device) through the arrangement of the pseudo bonding pad and the first interconnection structure, and when the dummy pin is connected with the pseudo bonding pad, static electricity accumulated on the dummy pin is transmitted to the electrostatic protection circuit through the pseudo bonding pad to be released. Therefore, static damage to the semiconductor chip (DRAM) caused by static gathering of the dummy pin is prevented.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to an electrostatic protection circuit. Background technique [0002] Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) is a semiconductor storage device commonly used in computers, and is composed of many repeated storage units. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage. [0003] The existing dynamic random access memory (DRAM) is usually packaged in a ball grid array (BGA, Ball Grid Array) manner during manufacture, but this packaging method usually b...

Claims

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Application Information

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IPC IPC(8): H01L23/60H01L23/31H01L27/02
CPCH01L23/60H01L23/3128H01L27/0248
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC
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