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Planarization insulating layer and manufacturing method

A manufacturing method and technology of insulating layers, which are applied in the manufacture of semiconductor/solid-state devices, electrical components, and electrical solid-state devices, etc., can solve the problems of metal residues, step difference of insulating layers, etc., and achieve the effect of improving yield and process accuracy.

Pending Publication Date: 2021-08-06
FUJIAN HUAJIACAI CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] Therefore, it is necessary to provide a planarized insulating layer and a manufacturing method to solve the problem that there is a level difference at the top of the insulating layer, which causes metal residues to easily occur in the level difference area.

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  • Planarization insulating layer and manufacturing method
  • Planarization insulating layer and manufacturing method
  • Planarization insulating layer and manufacturing method

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Embodiment Construction

[0068] In order to explain in detail the technical content, structural features, achieved goals and effects of the technical solution, the following will be described in detail in conjunction with specific embodiments and accompanying drawings.

[0069] see Figure 4 to Figure 15 , the present embodiment is a method for manufacturing a planarized insulating layer. The manufacturing method can be performed on a glass substrate, a plastic substrate or other substrates, and the substrate is used to carry various film layers. The method for making a planarized insulating layer includes the following steps: making a metal layer 2 on a substrate as a grid. Specifically, the metal layer material 21 is first deposited on the substrate, and the structure is as Figure 4 shown. The metal layer material 21 may be one or more metals with excellent electrical conductivity, such as aluminum, molybdenum, nickel, copper, silver, chromium, and alloys. Metal layer 2 is formed after metal lay...

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Abstract

The invention discloses a planarization insulating layer and a manufacturing method thereof. The planarization insulating layer comprises a metal layer and insulating layers; the metal layer is arranged on the substrate; the insulating layers comprise a lower insulating layer and an upper insulating layer, the lower insulating layer is arranged on the substrate and surrounds the metal layer, the top of the lower insulating layer is flush with the top of the metal layer, the upper insulating layer covers the lower insulating layer and the metal layer, and the top of the upper insulating layer is flat. According to the planarization insulating layer and the manufacturing method provided by the technical schemes of the invention, the tops of the insulating layers are kept at the same horizontal height, and the product quality is prevented from being affected. As the tops of the insulating layers are flat, the influence of the process compatibility caused by the difference between the thickness of a film layer at the segment difference and the thickness of a flat region is not needed to be considered later, the consistency of the line width and the spacing of each region of the substrate can be achieved, the process precision can be improved, and the yield can be improved.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a planarized insulating layer and a manufacturing method. Background technique [0002] Indium gallium zinc oxide (IGZO for short) is an amorphous oxide containing indium, gallium and zinc. The carrier mobility is 20 to 30 times that of amorphous silicon, which can greatly improve the pixel electrode of the transistor. The charging and discharging rate is high, the response speed of the pixel is improved, and the refresh rate of the panel is faster, which can realize the ultra-high resolution display panel. At the same time, the existing amorphous silicon production line can be compatible with the IGZO process only with minor modifications, so it is more competitive with low temperature polysilicon (LTPS) in terms of cost. [0003] However, the currently commonly used bottom-gate IGZO-TFT is sensitive to the material of the active layer, and the channel region is easily damaged...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/77H01L27/12H01L27/32
CPCH01L27/1288H01L27/1248H10K59/124
Inventor 陈宇怀
Owner FUJIAN HUAJIACAI CO LTD
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