A backside deep trench isolation process of fd-soi based on bonding process

Abstract

The present invention relates to the technical field of semiconductors, and discloses a back deep trench isolation process of FD-SOI based on a bonding process, by making M first bonding Pads on the uppermost metal wiring layer of the first chip, M second bonding Pads are made on the uppermost metal wiring layer of the second chip, and then the first chip and the second chip are aligned and bonded so that the M first bonding Pads on the first chip are aligned with the second bonding Pads. The M second bonding pads on the two chips are electrically connected one by one, which can reduce the area required for integrating the first chip and the second chip. In addition, the isolation groove in the first chip and the isolation in the second chip The trenches are arranged up and down to reduce the proportion of the isolation trench to the overall chip area, thereby reducing the chip area; finally, the second chip is made with deep trench isolation when making the through-hole layer, thereby greatly reducing the cost and cost of chip manufacturing. Period, while the evolution from shallow trench isolation to deep trench isolation enhances the isolation effect of chip devices.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a back deep trench isolation process of FD-SOI based on a bonding process. Background technique [0002] At present, in the chip manufacturing process, most of the different circuit modules on the chip are manufactured on different wafers according to the process technology, and then these circuit modules are tiled and integrated on the same base plate to realize the electrical properties of these circuit modules. connection, and finally package the bottom plate to form the final product. For example, it integrates the central processing unit CPU, random access memory RAM, read-only memory ROM, various I / O ports and interrupt systems, and timer / counter single-chip microcomputer chips. However, as the functions of the chip continue to increase, there are more and more circuit modules in the chip. If the circuit modules are still tiled on the bottom plate, the area of ​​the...

AI Technical Summary

Problems solved by technology

However if figure 1 As shown, the back bias voltage control terminal of the FDSOI transistor on the existing wafer is drawn from the wafer, and competes with the gate, source and drain for the metal interconnection area, and this structure often leads to a decrease in the chip area of ​​the FDSOI transistor. Larger than conventional bulk silicon or FinFET

[0004] In addition, in the manufacturing process of FDSOI-based chips, isolation trenches are first made on the wafer, then FDSOI transistors are made on the wafer, and finally back-bias via holes are made on the FDSOI transistors. According to the existing manufacturing process , when making isolation trenches, FDSOI transistors, and back-bias vias on the wafer, a photomask is required, which is costly, and further optimization of the chip manufacturing process is required to reduce manufacturing costs

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