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Method and arrangement for handling memory access for a tcf-aware processor

A memory access and processor technology, applied in the computer field, can solve the problems of slowing down the execution speed, low power consumption, increasing overhead, etc., and achieve the effect of high performance

Pending Publication Date: 2021-09-03
TEKNOLOGIAN TUTKIMUSKESKUS VTT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although SIMD is more cost-effective, easier to program, and its implementation features lower power consumption, it cannot efficiently execute code with controlled parallelism and heterogeneity among threads
Another dimension of the problem arises from the fact that in implementations of MIMD and SIMD architectures, the number of hardware threads is fixed, and there is an overhead when the number of software threads exceeds the supported number
This solution slows down execution - especially in case of low memory activity, partitions or partially optimized modes

Method used

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  • Method and arrangement for handling memory access for a tcf-aware processor
  • Method and arrangement for handling memory access for a tcf-aware processor
  • Method and arrangement for handling memory access for a tcf-aware processor

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Embodiment Construction

[0048] First, the ESM architecture will be reviewed. exist figure 1 , a high-level diagram of a scalable architecture emulating shared memory on a silicon platform is shown. It comprises a set of processors (cores) P1, P2, P3,..., Pp 102 connected to a physically distributed but logically shared (data) memory M1 via a physically scalable high-bandwidth interconnection network 108, M2, M3,..., Mp112. Active memory unit 110 associated with data store 112 may be considered a memory control logic unit for handling memory references. The active memory unit 110 is arranged to manage computations related to situations where multiple memory references are to the same memory location, for example during a multi(-prefix) operation, for example. Instruction memory modules I1 , I2 , I3 , . . . , Ip 104 are configured to carry program code for each processor 102 . To efficiently emulate shared memory through a distributed memory based implementation, the processor 102 is multi-threaded...

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PUM

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Abstract

An arrangement for handling shared data memory access for a TCF-aware processor. The arrangement comprises at least a flexible latency handling unit (601) comprising local memory (602) and related control logic, said local memory being provided for storing shared data memory access related data. The arrangement is configured to receive at least one TCF comprising at least one instruction, the at least one instruction being associated with at least one fiber, wherein the flexible latency handling unit is configured to determine if shared data memory access is required by the at least one instruction, if shared data memory access is required, send a shared data memory access request, via the flexible latency handling unit, observe, essentially continuously, if a reply to the shared data memory access request is received, suspend continued execution of the instruction until a reply is received, and continue execution of the instruction after receiving the reply so that the delay associated with the shared data memory access is dynamically determined by the actual required shared data memory access latency.

Description

technical field [0001] The present invention relates generally to computer technology. In particular, the invention relates to processor memory access. Background technique [0002] Relevant to software involving multithreaded computation, the organization of efficient cooperation among a large number of parallel threads has been a fundamental problem due to the limitations of current models. In V. Leppanen, M. Forsell, and J-M. Makela, "Thick Control Flows: Introduction and Prospects", Proceedings of the 2011 International Conference on Parallel and Distributed Processing Technology and Applications (PDPTA' 11), Las Vegas, USA, pp. 540–546, 2011 introduces the concept of parallel thick control flow (TCF) as a solution. When thick control flow (a fiber is similar to a thread in terms of number of fibers) executes a statement or expression of a program, all fibers are considered to execute the same program element synchronously and in parallel. The concept of thick control...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/52G06F9/38
CPCG06F9/522G06F9/3851G06F9/3887G06F9/3824G06F9/3888G06F9/3867G06F9/544
Inventor 马尔蒂·佛塞尔尤西·罗伊瓦伊宁
Owner TEKNOLOGIAN TUTKIMUSKESKUS VTT