SGT-MOSFET and manufacturing method thereof

Abstract

The invention belongs to the technical field of semiconductors, and discloses an SGT-MOSFET and a manufacturing method thereof. The method comprises the steps: depositing a masking layer on a substrate epitaxial layer, and photoetching a deep groove; removing the masking layer, growing a field oxide layer, and depositing shielding gate polycrystalline silicon; etching back shielding gate polycrystalline silicon, and photoetching a shallow groove; and photoetching a field oxide layer, forming a gate groove, growing a gate oxide layer, depositing gate polycrystalline silicon, performing back etching, and performing subsequent manufacturing. According to the invention, a new manufacturing method is adopted to connect the shield gate polycrystalline silicon and the gate polycrystalline silicon contact hole; and the manufacturing method adopted by the invention does not involve a photoetching process of shield gate polycrystalline silicon and grid polycrystalline silicon, and the shield gate polycrystalline silicon and the grid polycrystalline silicon are basically flush with the surface of the silicon substrate after being etched, so that the height difference of the polycrystalline silicon is eliminated, and the shield grid polycrystalline silicon and the grid polycrystalline silicon are punched well without generating the risk of bridging of the shield grid polycrystalline silicon and the grid polycrystalline silicon.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to an SGT-MOSFET and a manufacturing method thereof. Background technique [0002] At present, the traditional process steps of SGT are as simple as: first etch the epitaxial layer to form a deep trench, then grow a field oxide layer in the deep trench, and then fill the shielding gate polysilicon; then etch the field oxide layer to form a gate trench, Then a gate oxide layer is grown and filled with polysilicon to form a gate; finally, ion implantation in the well region and ion implantation in the source region form the source. For the specific SGT structure, see the top view and cross-sectional view of the SGT structure in the accompanying drawings. [0003] As the size of the device continues to shrink, due to the limitation of the size of the contact hole, it becomes more and more difficult to make a hole connection on the shielded gate polysilicon and the g...

AI Technical Summary

Problems solved by technology

The disadvantage of this approach is that the height difference between the shielded gate polysilicon and the gate polysilicon is caused by photolithography on the wafer surface, and the height difference is about 1um, which will affect the subsequent photolithography process of the contact hole.

On the one hand, the height difference of polysilicon will affect the accuracy of contact hole exposure; on the other hand, since the length of the contact hole on the gate polysilicon, shield gate polysilicon, and substrate silicon surface is not the same, it will increase the contact hole etching. process complexity

[0004] Through the above analysis, the existing problems and defects of the prior art are: in the prior art, due to the height difference of the polysilicon on the surface of the wafer due to etching, it is easy to affect the photolithography process of the subsequent contact hole

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