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MOSFET device with super junction structure and preparation method of MOSFET device

A device, N-type technology, applied in the field of MOSFET devices with superjunction structure and their preparation, can solve the problems affecting the switching speed performance of the device, fast reverse recovery current change, electromagnetic interference, etc., to improve the soft recovery performance, soft The effect of increasing the recovery effect and reducing the lifespan

Pending Publication Date: 2021-10-19
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the reverse recovery current of the existing MOSFET devices changes quickly and the softness is poor, which will cause shortcomings such as oscillation and electromagnetic interference, which will affect the switching speed and performance of the device

Method used

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  • MOSFET device with super junction structure and preparation method of MOSFET device
  • MOSFET device with super junction structure and preparation method of MOSFET device
  • MOSFET device with super junction structure and preparation method of MOSFET device

Examples

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Embodiment 1

[0045] See figure 1 , figure 1 It is a schematic diagram of a MOSFET device with a super junction structure provided by an embodiment of the present invention, which includes:

[0046]A semiconductor layer, which includes an N++ substrate region 1, an N-type buffer layer, and an N-type epitaxial layer 5 from bottom to top;

[0047] A plurality of P-type body regions 6 arranged at intervals horizontally, located on the upper surface of the N-type epitaxial layer 5 in the semiconductor layer;

[0048] The N+ implantation region 7 is located on both sides of the upper surface of the P-type body region 6;

[0049] The P+ contact region 8 is located at the center of the upper surface of the P-type body region 6;

[0050] The gate 11 is located on the upper surfaces of two adjacent P-type body regions 6, and is separated from the P-type body regions 6 by a gate insulating film 9;

[0051] The source 12 covers the gate 11 and is separated from the gate 11 by an interlayer insulat...

Embodiment 2

[0073] On the basis of the first embodiment above, this embodiment provides a method for fabricating a MOSFET device with a super junction structure, please refer to figure 2 , figure 2 It is a flow chart of a method for manufacturing a MOSFET device with a super junction structure provided by an embodiment of the present invention, specifically including the following steps:

[0074] S1: Epitaxial growth of N-type buffer layer on N++ substrate;

[0075] S2: epitaxially growing N-type epitaxial layers multiple times on the N-type buffer layer, and selectively implanting P-type impurities after each growth, to form a semiconductor layer having several first columnar layers and second columnar layers;

[0076] S3: performing P-type impurity implantation on the upper surface of the N-type epitaxy to form a P-type body region, and respectively performing N-type impurity implantation and over-P-type impurity implantation on the P-type body region to form an N+ implantation regio...

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Abstract

The invention discloses an MOSFET device with a super junction structure and a preparation method of the MOSFET device. The device comprises a semiconductor layer, a plurality of P-type body regions horizontally arranged at intervals, N + injection regions, P + contact regions, grid electrodes, source electrodes and drain electrodes; the semiconductor layer comprises an N + + substrate region, an N-type buffer layer and an N-type epitaxial layer from bottom to top; the plurality of P-type body regions are positioned on the upper surface of the N-type epitaxial layer in the semiconductor layer; the N + injection regions are located on the two sides of the upper surface of each P-type body region; the P + contact regions are positioned in the centers of the upper surfaces of the P-type body regions respectively; the grid electrodes are located on the upper surfaces of the two adjacent P-type body regions and are separated from the P-type body regions through grid electrode insulating films; the source electrodes cover the grid electrodes and spaced apart from the grid electrodes by interlayer insulating films; the drain electrodes are positioned on the lower surfaces of the N + + substrate region in the semiconductor layer; the semiconductor layer is also internally provided with a trap level region formed by charged particles, and the trap level region is located at a position, close to the N-type buffer layer, of the lower part of the N-type epitaxial layer. The MOSFET device provided by the invention has relatively good soft recovery performance and relatively high switching speed.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a MOSFET device with a super junction structure and a preparation method thereof. Background technique [0002] Power semiconductor devices, also known as power electronic devices, are used in almost all electronic manufacturing industries, such as computer fields, consumer electronics fields, and industrial control fields. With the continuous improvement of the demand for electronic products and energy efficiency requirements, the performance requirements for power devices are also getting higher and higher. The performance of power devices determines the technical level of power system applications. At the same time, applications put forward higher requirements for power devices, which promotes the development of new power devices. [0003] The traditional IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) is widely used in power dev...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/08H01L29/417H01L29/739H01L29/78H01L21/28H01L21/336H01L21/331
CPCH01L29/7827H01L29/66666H01L29/66333H01L29/7398H01L29/0684H01L29/0634H01L29/0821H01L29/41708H01L29/401
Inventor 何艳静侯敏袁嵩江希弓小武
Owner XIDIAN UNIV