MOSFET device with super junction structure and preparation method of MOSFET device
A device, N-type technology, applied in the field of MOSFET devices with superjunction structure and their preparation, can solve the problems affecting the switching speed performance of the device, fast reverse recovery current change, electromagnetic interference, etc., to improve the soft recovery performance, soft The effect of increasing the recovery effect and reducing the lifespan
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Embodiment 1
[0045] See figure 1 , figure 1 It is a schematic diagram of a MOSFET device with a super junction structure provided by an embodiment of the present invention, which includes:
[0046]A semiconductor layer, which includes an N++ substrate region 1, an N-type buffer layer, and an N-type epitaxial layer 5 from bottom to top;
[0047] A plurality of P-type body regions 6 arranged at intervals horizontally, located on the upper surface of the N-type epitaxial layer 5 in the semiconductor layer;
[0048] The N+ implantation region 7 is located on both sides of the upper surface of the P-type body region 6;
[0049] The P+ contact region 8 is located at the center of the upper surface of the P-type body region 6;
[0050] The gate 11 is located on the upper surfaces of two adjacent P-type body regions 6, and is separated from the P-type body regions 6 by a gate insulating film 9;
[0051] The source 12 covers the gate 11 and is separated from the gate 11 by an interlayer insulat...
Embodiment 2
[0073] On the basis of the first embodiment above, this embodiment provides a method for fabricating a MOSFET device with a super junction structure, please refer to figure 2 , figure 2 It is a flow chart of a method for manufacturing a MOSFET device with a super junction structure provided by an embodiment of the present invention, specifically including the following steps:
[0074] S1: Epitaxial growth of N-type buffer layer on N++ substrate;
[0075] S2: epitaxially growing N-type epitaxial layers multiple times on the N-type buffer layer, and selectively implanting P-type impurities after each growth, to form a semiconductor layer having several first columnar layers and second columnar layers;
[0076] S3: performing P-type impurity implantation on the upper surface of the N-type epitaxy to form a P-type body region, and respectively performing N-type impurity implantation and over-P-type impurity implantation on the P-type body region to form an N+ implantation regio...
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Abstract
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