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Cap layer etching optimization method

An optimization method and etching technology, which is applied in the direction of microlithography exposure equipment, photoplate making process coating equipment, lasers, etc., can solve the problem of Caplayer layer damage, affecting the photoelectric characteristics and reliability of the chip, and the edge of the optical film and the metal cannot be closely attached In order to achieve the effect of increasing the selection ratio, facilitating the etching angle, and facilitating the control

Pending Publication Date: 2021-11-19
威科赛乐微电子股份有限公司
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, in the current metal deposition step, the edge metal deposited on the Cap layer cannot be closely attached to the optical film, and there will be certain gaps (such as figure 1 SEM picture), when using SN830 solution to clean the residual photoresist, the SN830 solution is very easy to soak into the Cap layer from the gap, dissolve part of the Cap layer, cause certain damage to the Cap layer, and finally affect the chip. Optoelectronic characteristics and reliability
[0004] Therefore, it is urgent to solve the problem that the edge of the optical film cannot be closely attached to the metal during metal deposition, and seek a method that can protect the Cap layer layer from etching

Method used

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Embodiment

[0042] Example: Figure 2-5 As shown, a CAP Layer layer 3 etch optimization method includes the following steps:

[0043] S1, preparing the overall of the whole structure; the total structure of the epitaxial sheet 1 includes a CAP Layer layer 3, a P-DBR layer, an oxide layer, a quantum well layer, an N-DBR layer, and a substrate. The substrate is a GaAs single crystal substrate.

[0044] S2, warp compensation processing of the N-plane of the epitaxial sheet 1; the warpage compensation is to grow a layer of stress film 2, the material of the stress film 2 is SiO 2 Sin X SiO X N y The stress film 2 is used to compensate for the epitaxial tabs, so that the epitaxial sheet 1 is flat, facilitating the procedure such as photolithography, metal deposition.

[0045] S3, a layer of optical film 4 is deposited on the CAP Layer layer 3 of the P-surface of the epitaxial sheet 1; the material of the optical film is one of the dielectric formed by Si, N, O, Al, F, Mg or Several forming composit...

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Abstract

The invention discloses a Cap layer etching optimization method. The method comprises the following steps: S1, preparing an epitaxial wafer of a full structure; S2, carrying out warping compensation on the N surface of the epitaxial wafer; S3, depositing a layer of optical film on the Cap layer on the P surface of the epitaxial wafer; S4, performing ohmic contact photoetching on the epitaxial wafer deposited with the optical film to enable the edge of the photoresist to have an inclination angle; S5, etching off the optical film beyond the coverage range of the photoresist by using dry etching; S6, carrying out ohmic contact metal deposition, and depositing metal in the etched area, so that the deposited metal is in close contact with the dip angle of the edge of the photoresist and the Cap layer; and S7, removing the photoresist by using an SN830 solution. Through the process method, the deposited metal is tightly attached to the photoresist, the phenomenon that an SN830 solution etches the Cap layer is avoided, the selection ratio is increased, the etching angle is conveniently controlled, the yield of the chip is improved, and the performance of the chip is greatly protected.

Description

Technical field [0001] The present invention relates to the field of chip preparation, and more particularly to a CAP Layer layer etch optimization method. Background technique [0002] The VCSEL chip is made of an excess delay as a base film, and the corresponding process flow is made on the epitaxial sheet. The epitaxial sheet consists of a Cap Layer layer, a P-DBR, N-DBR, a oxide layer, a quantum well and a substrate, which will affect the reliability or photoelectric properties of the chip. [0003] During the preparation of the VCSEL chip, when the optical film deposition, photolithography, etching, etching and metal deposition is performed on the CAP Layer layer of the epitaxial piece, and the Sn830 solution is used to wash the epitaxial sheet, and the residual remaining in the epitaxial LED in the film. Among them, the photolithography process is to remove partial photoresist, exposing the optical film; the etching step is to remove the optical film of the photolithography...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01S5/028H01S5/183G03F7/20G03F7/16
CPCH01S5/0282H01S5/183G03F7/70425G03F7/162
Inventor 王田瑞王凤玲成飞
Owner 威科赛乐微电子股份有限公司