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Method for overcoming photoetching development defect of NAND flash memory source region

An active area, lithography technology, applied in the manufacturing of electrical components, electric solid-state devices, semiconductor/solid-state devices, etc., can solve the problems of residues, development residues, device defects, etc., to improve performance and avoid development defects. Effect

Pending Publication Date: 2021-11-30
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology

[0004] The object of the present invention is to provide a method for improving the photolithography and development defects of the NAND flash memory active area, which can avoid the development residue remaining between the side walls in the core active area due to the large aspect ratio of the gap between the side walls problems in the gap, which in turn can solve the problem of device defects caused by photoresist development residues in the core active area

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  • Method for overcoming photoetching development defect of NAND flash memory source region
  • Method for overcoming photoetching development defect of NAND flash memory source region
  • Method for overcoming photoetching development defect of NAND flash memory source region

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Embodiment Construction

[0035] The method for improving photolithography and development defects in the active region of NAND flash memory proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0036] The current manufacturing process of existing NAND flash memory usually includes the following steps: first, as Figure 1a As shown, a floating gate layer 200, a gate oxide layer 300, a hard mask layer 400, an amorphous silicon layer 500 and other multi-layer films and a core layer are deposited on a substrate 100 having a core active region I and a peripheral region II (including the first o...

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Abstract

The invention provides a method for overcoming a photoetching development defect of an NAND flash memory source region, which is applied to the field of semiconductors, and is characterized in that an organic dielectric layer is filled in a side wall gap with a high aspect ratio of a core active region to prevent photoresist from being in direct contact with a side wall, sthe photoresist is coated on the organic dielectric layer, so that when exposure and development are carried out to form the patterned photoresist layer, development residues left in the gaps of the side walls after photoresist development are avoided, and generation of photoresist development defects can be further avoided. Furthermore, the top surface of the organic dielectric layer is flush with the top surface of the side wall, so that the side wall and the organic dielectric layer which are equal in height can be used as masks for continuous downward etching subsequently, and the quality of a pattern formed in the to-be-patterned layer is ensured.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for improving photolithography and development defects in the active region of NAND flash memory. Background technique [0002] NAND flash (flash memory) memory array is usually composed of multiple blocks, and each block contains several word lines and selection transistors. It has the advantages of large capacity, long life, non-volatility and low cost, so it is widely used in automobiles, Electronics, life products. In order to meet the ever-increasing demand for storage capacity, the size of word lines has been shrinking continuously with the advancement of technology. Therefore, the process requirements are getting higher and higher. [0003] In the process of developing the two-dimensional planar NAND flash product process of the technology node of 19 nanometers and below, the aspect ratio of the sidewall of the memory array used to make the core active ar...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/308H01L27/11524H10B41/35
CPCH01L21/3081H01L21/3086H10B41/35
Inventor 刘天舒巨晓华王奇伟
Owner SHANGHAI HUALI MICROELECTRONICS CORP