Enhanced GaN-based HEMT device
An enhanced and device technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of large fluctuations in the threshold voltage of devices, incomplete pinch-off of the channel, leakage, etc., to suppress the offset of the threshold voltage and ensure Surface morphology, cost reduction effect
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0055] The thickness of the GaN buffer layer in the test device is 4 μm, and the thickness of the GaN channel layer is 150 nm. The thickness of the AIN insertion layer is 1.2 nm, the thickness of the AlGaN barrier layer is 25 nm, and Al accounts for 30% of the total mass, GaN cap layer The thickness is 3 nm. When the etch parameter is 15W, the source power is 50W, CL 2 The flow rate is 4SCCM, BCL 3 The flow rate is 10sccm. The thickness of the AIN interface protective layer and the insulated gate dielectric layer is 4 nm and 14 nm, respectively, and the drain voltage is biased to 0.1V. The Ti / Al / Tin alloy was sputtered using a magnetron sputtering instrument, and the thickness of each layer was 25 / 150 / 100 nm, respectively, and the annealing temperature was 500 degrees Celsius, and the annealing time was 30 seconds.
[0056] Measure the maximum field effect mobility of this embodiment is 201cm 2 / V · S, when leakage current reaches 10 -3 When MA / mm, the threshold offset volt...
Embodiment 2
[0058] Relative to Examples, this embodiment has no AIN interface protective layer, reference Image 6 Described that the LPCVD high temperature process has adverse effects on the etching interface below the gate electrode, increasing the roughness of the surface of the sample, and by 93 cm by the 2Deg mobility 2 / V · S, below the Example 1, indicating that the LPCVD high temperature process causes degradation of the device 2DEG mobility.
[0059] When the leakage current reaches 10 -3 When the MA / mm, the threshold offset voltage is 0.15V, indicating that due to the lack of a AIN interface protection layer, the embodiment has the maximum threshold voltage offset, indicating that the high-temperature LPCVD process will produce high-density traps at the etching interface. Electron, causing the trap concentration faced from the device etching, suppressing the offset of the threshold voltage.
[0060] The breakdown voltage of this embodiment is 401V, which is lower than the embodime...
Embodiment 3
[0062] refer to Figure 7 However, with respect to the exempted terminal, the breakdown voltage 243V, with respect to the embodiment one, the slot terminal can alleviate the electric field concentration, improve the average electric field strength of the device and increase the breakdown voltage.
[0063] Therefore, the present invention etch the tank terminal structure while the groove gate structure is etched, so that at least the groove terminal structure retains at least 10 nm AlGa barrier layers to ensure that there is still a high concentration 2deg, and passed the test It is found that the tank terminal can alleviate the electric field concentration, improve the average electric field strength of the device and increase the breakdown voltage. By increasing the AIN interface protective layer and the insulated gate dielectric layer, the surface morphology is ensured, and the AIN interface protective layer can suppress the offset of the threshold voltage. By making the source e...
PUM
| Property | Measurement | Unit |
|---|---|---|
| thickness | aaaaa | aaaaa |
| thickness | aaaaa | aaaaa |
| thickness | aaaaa | aaaaa |
Abstract
Description
Claims
Application Information
Login to View More 


