Preparation method of enhanced device based on GaN-HEMT
An enhanced, device technology, applied in the field of preparation, can solve problems such as leakage, device threshold voltage fluctuations, channel can not be completely pinched, etc., to achieve cost reduction, good etching effect, good roughness effect
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[0038] A method for preparing an enhanced device based on GaN-HEMT of the present invention is used to prepare an enhanced device for GaN-HEMT, refer to Figure 10 ,include:
[0039] S1. Form a silicon-based GaN epitaxial wafer, including a P-type substrate 10, a GaN buffer layer 20, a GaN channel layer 30, an AlN insertion layer 40, an AlGaN barrier layer 50 and a GaN cap layer 60 from bottom to top.
[0040] S2 , implementing an etching process to realize the grooved gate structure 70 .
[0041] S3, generating a protective layer for the etching interface.
[0042] S4 , making the source electrode 1 , the drain electrode 2 and the gate electrode 3 .
[0043] Specifically, a silicon-based GaN epitaxial wafer is formed in S1, which sequentially includes a P-type substrate 10, a GaN buffer layer 20, a GaN channel layer 30, an AlN insertion layer 40, an AlGaN barrier layer 50, and a GaN cap layer 60 from bottom to top. . Among them, the thickness of the GaN buffer layer 20 is...
Embodiment 1
[0065] The thickness of the GaN buffer layer in the test device is 4 μm, the thickness of the GaN channel layer is 150 nm, the thickness of the AlN insertion layer is 1.2 nm, the thickness of the AlGaN barrier layer is 25 nm and Al accounts for 30% of the total mass, the GaN cap layer The thickness is 3nm. The etching parameters are when the bias power is 15W, the source power is 50W, Cl 2 The flow rate is 4sccm, BCl 3 The flow rate is 10sccm. The thicknesses of the AIN interface protection layer and the insulating gate dielectric layer are 4nm and 14nm respectively, and the drain voltage bias is set to 0.1V. The Ti / Al / TiN alloy is sputtered by a magnetron sputtering device, and the thickness of each layer is 25 / 150 / 100 nm respectively, the annealing temperature is 500 degrees Celsius, and the annealing time is 30 seconds.
[0066] The maximum field-effect mobility measured to obtain this embodiment is 201cm 2 / V·s, when the leakage current reaches 10 -3 At mA / mm, the thr...
Embodiment 2
[0068] With respect to embodiment one, this embodiment has no AIN interface protective layer, refer to Figure 6 , indicating that the high temperature process of LPCVD has an adverse effect on the etching interface below the gate electrode, increasing the roughness of the sample surface, and the 2DEG mobility is 93cm 2 / V·s is lower than that in Example 1, indicating that the high temperature process of LPCVD causes the degradation of the 2DEG mobility of the device.
[0069] When the leakage current reaches 10 -3 At mA / mm, the threshold shift voltage is 0.15V, indicating that due to the lack of AIN interface protection layer, this embodiment has the largest threshold voltage shift, indicating that the high-temperature LPCVD process will generate high-density trap trapping channels at the etching interface The electrons cause the concentration of traps out of the etched interface of the device, and suppress the shift of the threshold voltage.
[0070] The breakdown voltage ...
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