Storage array manufacturing method and circuit for improving word line edge defects and application of storage array manufacturing method and circuit

Abstract

The invention relates to the technical field of semiconductor manufacturing, and discloses a memory array manufacturing method for improving word line edge defects, a circuit and application thereof, the method comprises the following steps: setting a redundant bit line, matching and manufacturing a photomask of the bit line according to an edge region of the redundant bit line at least covering a memory array unit word line, preparing a bit line layer of a memory array unit, depositing to form a polycrystalline silicon layer for manufacturing a word line, and manufacturing a word line layer by using a photomask of the word line. According to the invention, the defect of fracture of the edge of the word line can be effectively improved without increasing the working procedures and the chip area, the yield of the chip is greatly improved, and the method has practical value in practical significance.

Description

Technical field [0001] The present invention relates to the field of semiconductor manufacturing technology, particularly relates to an improved line edge defects word memory array manufacturing method, a circuit and applications thereof. Background technique [0002] Conventional floating gate type flash memory design process, the memory cell array in the vertical and lateral four sides usually of 4-6 reserved for redundant bit line (Dummy BL) 4 to 6, and the redundant word line (Dummy WL ) design, the main purpose of the actual production of integrated circuits in the wafer, produced when the memory cell array bit line or a word line when a layer step, since there is no memory cell peripheral array pattern, so that most cells of the memory array pattern exposure process is easy because the edges or etching process unevenness leads to some drawbacks, so at the time of circuit design 4 to 6 adds redundant bit lines and redundant 4 to 6 to avoid these word lines possible defects, ...

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Problems solved by technology

[0003] In general, the edge of the word line of the memory array unit needs to be connected to the transmission current voltage of the contact hole to operate the connected memory cell, but in the actual production process, we found that the current design method is easy to produce the edge of the word line. The polysilicon that carries the function of the word line has a certain probability of breaking, and the edge of the word line needs to be connected to the metal layer through a contact hole, which will cause the connected memory cells to fail

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