Three-dimensional monolithic integrated circuit structure and preparation method thereof
A monolithic integrated circuit, three-dimensional technology, applied in the direction of circuits, electrical components, electrical solid devices, etc., to achieve high reliability, strong construction, and improve the effect of heat dissipation
Active Publication Date: 2022-01-07
MICROTERA SEMICON (GUANGZHOU) CO LTD
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Problems solved by technology
[0003] However, due to the complex composition of three-dimensional integration, the heat dissipation problem of M3D has always attracted much attention, and the reliable application of M3D also needs to be based on its good heat dissipation
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Embodiment 1
[0036] An embodiment of a method for preparing a three-dimensional monolithic integrated circuit structure, such as figure 1 shown, including the following steps:
[0037] (1) On the 22nm process line width device production line, use an N-type substrate 1 of an 8-inch silicon wafer (doping concentration 10 14 ~10 16 cm -3 ) is deposited on a silicon oxide layer 2 with a thickness of 25nm by wet oxidation;
[0038] (2) H-bond 3 is formed between the substrate and the silicon oxide layer by hydrogen ion implantation;
[0039] (3) Holes are formed on the surface of the silicon oxide layer by photolithography and dry etching;
[0040] (4) Embed carbon nanotubes in the cavity by spraying, and then inject TEOS into the top of the cavity to fix it, forming a heat dissipation layer 5 containing carbon nanotubes;
[0041] (5) Surface planarization (chemical mechanical polishing) and cleaning of the silicon oxide layer and the surface of the cavity;
[0042] (6) In a vacuum envir...
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Abstract
The invention discloses a three-dimensional monolithic integrated circuit structure and a preparation method thereof, and belongs to the field of integrated circuits. According to the preparation method of the three-dimensional monolithic integrated circuit structure, cavities are formed in gaps of a device layer, and a carbon nanotube material with high heat dissipation performance is introduced into the cavities to serve as a heat dissipation base body, so that the temperature requirement of low-temperature bonding of the device layer is met, and the heat dissipation performance of the whole integrated circuit is improved. Meanwhile, the device layer is isolated in an independent silicon island by an STI layer through the structural design, so that the complexity of circuit design and integrated circuit structure preparation is not increased. The method can be used for preparing a three-dimensional monolithic integrated circuit structure with multiple layers of carbon nanotube-containing film structures according to production application requirements, and is high in constructability and high in reliability. The invention also discloses a three-dimensional monolithic integrated circuit structure prepared by the preparation method of the three-dimensional monolithic integrated circuit structure.
Description
technical field [0001] The invention relates to the field of integrated circuits, in particular to a three-dimensional monolithic integrated wafer structure and a preparation method thereof. Background technique [0002] "Moore's Law" has always been leading the development of integrated circuits. However, due to the bottleneck of existing lithography technology, interconnection delay and process fluctuations, the application of "Moore's Law" is approaching the physical limit. In order to further improve the integration of existing products and reduce the interconnection delay, the research of three-dimensional monolithic integration (M3D) has become a development trend. The so-called M3D means that the upper-layer devices are manufactured vertically in sequence after the lower-layer devices are manufactured, and the devices of each layer are bonded through interlayer deposition to achieve wafer bonding, and through-holes between monolithic layers are vertically interconnect...
Claims
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IPC IPC(8): H01L21/822H01L21/762H01L23/373
CPCH01L21/8221H01L21/76224H01L23/373
Inventor 刘森刘盛富史林森李建平班桂春
Owner MICROTERA SEMICON (GUANGZHOU) CO LTD