Video denoising hardware implementation method based on FPGA

Abstract

The invention discloses a video denoising hardware implementation method based on an FPGA (Field Programmable Gate Array), which comprises the following steps of: mapping video data to an internal memory of the FPGA by utilizing a ping-pong cache structure to obtain a current frame image; calculating a difference value residual error threshold value and a motion vector threshold value of the reference frame and the current frame for the current frame after Gaussian smoothing, comparing a pixel residual error value of the reference frame and the current frame with the difference value residual error threshold value of the reference frame and the current frame, and comparing a motion tensor value with the motion vector threshold value to divide a current frame image area into a background area and a foreground area; performing time domain noise reduction on the background region, and performing space domain noise reduction on the foreground region; and finally, outputting the denoised image to the FPGA, and storing the denoised image into an external memory to serve as a reference frame image of the next frame. According to the invention, the motion vector threshold and the difference residual threshold of the reference block and the current block replace a simple threshold to carry out dynamic multi-threshold segmentation, and the image is divided into the background region and the foreground region, so that the accuracy of region discrimination is improved.

Description

technical field [0001] The invention belongs to the technical field of image processing, in particular to an FPGA-based video denoising hardware implementation method. Background technique [0002] Field Programmable Gate Arrays (FPGAs) are increasingly used for the implementation of video processing applications. This is especially true for real-time embedded applications where latency and power consumption are important considerations. As image data is streamed from the sensor, the FPGA embedded in the smart camera is able to perform most of the image processing directly, and the camera provides a stream of processed output data rather than a sequence of images. The video data of smart cameras will inevitably be damaged by random noise in the process of collection, processing and transmission. Various noises not only affect the visual quality and produce bad visual experience, but also prevent users from obtaining real and correct information, and even Make the user misi...

AI Technical Summary

Problems solved by technology

[0003] The current time-space domain joint video denoising method has problems to be solved. First, it only focuses on the performance of the software algorithm, which is optimized for serial processors. There is no good FPGA hardware architecture, it is not suitable for parallel processing, and the actual running speed is relatively slow; The second is that the video frame is usually divided into motion areas and static areas by using a single threshold, which lacks a good degree of discrimination.

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