Preparation method of semiconductor memory, and semiconductor memory

Abstract

The invention relates to a preparation method of a semiconductor memory, and the semiconductor memory, and relates to the technical field of semiconductors. The method comprises the following steps: providing a semiconductor substrate, and forming transistors arranged in an array mode in the semiconductor substrate; forming a thin film stacking structure on the semiconductor substrate; forming a through hole penetrating through the thin film stacking structure, and exposing a source electrode of the transistor; epitaxially growing a storage node contact layer on the exposed surface of the source electrode of the transistor; and forming a lower electrode of a capacitor on the surface of the storage node contact layer. According to the scheme provided by the embodiment of the invention, the source electrode of the transistor is directly exposed by enabling the through hole to penetrate through the thin film stacking structure, and only one-time photomask alignment of the storage unit and the active region is needed, so that a large number of preparation processes can be saved.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductors, and in particular, to a method for manufacturing a semiconductor memory and the semiconductor memory. Background technique [0002] A storage cell (Storage Cell, hereinafter referred to as Cell) in a semiconductor memory such as DRAM (Dynamic Random Access Memory, Dynamic Random Access Memory) uses a storage capacitor (Storage Capacitor, hereinafter referred to as capacitor) to store bit (Bit) information. From a theoretical point of view, the simplest DRAM Storage Cell that stores a Bit of information includes the following four parts: Storage Capacitor, which uses the amount of charge stored in it, or the sum of the voltage difference between the two ends of the capacitor Low, to represent logical 1 and 0; Transistor, the transistor, its on and off, determines whether to allow or prohibit the reading and rewriting of the information stored in the Storage Capacitor; Wordline, the...

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Problems solved by technology

In this way, the bottom of the Cell needs to be aligned with the storage node pad, the storage node pad and the storage node, and the storage node and the active area. The process is complex and difficult to control.

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