Double-sampling single-refreshing method based on three-phase two-level topological structure

Abstract

The invention discloses a double-sampling single-refreshing method based on a three-phase two-level topological structure, and the three-phase two-level topological structure comprises a three-phase fully-controlled rectifier bridge, a DC bus capacitor, a three-phase fully-controlled inverter bridge, an LCL filter circuit at a rectification side, an LCL filter circuit at an inverter side, and a series transformer coupled with a power grid voltage. The controller DSP generates a modulation wave through operation and generates a PWM signal after PWM modulation to control the on-off state of the three-phase full-control inverter bridge, specifically, the controller DSP generates the modulation wave through operation, a comparison threshold value of the amplitude of the modulation wave is set in the controller DSP, the modulation wave is sampled at the wave crest and the wave trough of a carrier wave, and the carrier wave is sampled at the wave crest and the wave trough of the carrier wave; and comparing a modulation wave amplitude value obtained by actual sampling with a comparison threshold value to determine a refreshing loading moment. According to the method, the problem of digital control delay is effectively eliminated, and the adverse effect of control delay on the system is solved.

Description

technical field [0001] The invention relates to the technical field of power electronics, in particular to a double-sampling single-refresh method based on a three-phase two-level topological structure. Background technique [0002] With the application and development of power electronic equipment, digital control based on power electronic equipment has been widely used and developed due to its superior performance. It has been widely used in grid-connected inverters, energy storage converters and power management equipment. However, due to the inherent sampling delay and PWM delay of digital control, the control bandwidth of the system is severely limited, and the steady-state and dynamic performance of the system are also affected. [0003] Conventionally used methods to reduce control delay mainly include the method of peak and valley double-sampling refresh, the method of sampling time close to the refresh time, and the method of multiple sampling refresh. The double-...

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Problems solved by technology

The double-sampling refresh of peaks and valleys is to implement sampling at both peaks and valleys of the carrier wave, and the modulated wave calculated by the current sampling is updated at the next sampling time, which is still a delayed sampling method in essence, with a delay of half a carrier cycle; multiple sampling and The method of sampling time close to the refresh time can effectively reduce the control delay, but the sampling time of the inductor current is not at the average value of the ripple of the inductor current, which will introduce switching noise and affect the control of the system; research, but the control depends on the accuracy of the system's control model, and changes in actual system hardware parameters are likely to produce prediction deviations that affect the stability of the system

Although the above-mentioned method reduces the control delay to a certain extent, it does not completely eliminate the control delay, and still has a certain impact on the stability margin of the system.

[0004] The modulation process of double sampling and double refresh commonly used in the prior art to solve the problem of sampling calculation delay limiting the maximum duty cycle can be found in figure 1 shown in the figure V tri is the peak value of the carrier triangle wave, V inv is the inverter output voltage of the topology bridge arm, V m It is the modulating wave, here it is defined that the modulating wave is greater than the carrier V tri When the PWM output is positive logic, the inverter outputs a high level, that is, the duty cycle is proportional to the modulation wave; define the modulation wave obtained by refreshing immediately after the peak and valley sampling without control delay as V m1 ; But the actual situation is because of the sampling and calculation delay of the DSP processor, there will be a sampling calculation delay T after the peak and valley sampling d , the modulated wave obtained after delay is V m2

[0005] Sampling calculation delay T d The existence of limit the size of the maximum output duty cycle, the figure shows the modulation state when the modulation amplitude is positive, as shown in section ③, due to the sampling calculation delay time T d The time greater than 50% of the negative duty cycle causes the modulation wave to intersect with the carrier before the modulation wave is updated, thus limiting the maximum output duty cycle; when the modulation wave amplitude is negative, when the modulation wave amplitude is greater than To a certain extent, when the modulation wave is calculated and updated in the valley sampling, it will also intersect with the carrier before the modulation wave is updated; based on this, it can be seen that the delay time of sampling calculation limits the size of the duty cycle and cannot achieve 0%-100 % range change

Since the sampling delay limits the range of the duty cycle, figure 2 The modulation method of double sampling and double refresh in the middle adopts the method of lagging one beat to refresh the modulation wave, that is, the modulation wave calculated in the current sampling period is not refreshed immediately but immediately refreshes the modulation wave at the beginning of the next sampling period, although it is solved The problem of duty cycle limitation, but there is still a one-beat control delay that affects the bandwidth and stability margin of the system

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