Three-dimensional fan-out wafer level packaging method and packaging structure

A wafer-level packaging, fan-out technology, applied in the manufacturing of electrical components, electric solid-state devices, semiconductor/solid-state devices, etc., can solve the problems of high cost, high technology and equipment, and achieve simple process technology, short process, The effect of low production cost

Pending Publication Date: 2022-04-19
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Highly difficult and complex TSV and TMV processes require higher technology and equi

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  • Three-dimensional fan-out wafer level packaging method and packaging structure
  • Three-dimensional fan-out wafer level packaging method and packaging structure
  • Three-dimensional fan-out wafer level packaging method and packaging structure

Examples

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Example Embodiment

[0041] Example 1

[0042] The present invention provides a three-dimensional fan-out wafer-level packaging method and packaging structure, for convenience in description, the following is described in a single chip 401 package above the wafer 402, such as Figure 1 as shown.

[0043] The present invention provides a three-dimensional fan-out wafer level packaging method, comprising the following steps:

[0044] Offers such as Figure 2 The IC wafer shown, by seed layer deposition, electroplating process in the chip pin position to produce chip copper column bump 202, the chip copper column bump height >3μm, structure such as Figure 3 shown;

[0045] The IC wafer is split into a single bare chip 201 by mechanical cutting or dry etching, e.g Figure 4 shown;

[0046] Providing a glass carrier plate 301, the surface of the glass carrier plate 301 is successively coated with a temporary bonding laser reaction layer 302 and a temporary bonding adhesive 303; wherein the thickness of the g...

Example Embodiment

[0058] Example 2

[0059] The present invention provides a three-dimensional fan-out wafer-level packaging method that enables multi-layer stacking; the specific steps are as follows:

[0060] Offers such as Figure 2 The IC wafer shown, by seed layer deposition, electroplating process in the chip pin position to produce chip copper column bump 202, the chip copper column bump height >3μm, structure such as Figure 3 shown;

[0061] The IC wafer is split into a single bare chip 201 by mechanical cutting or dry etching, e.g Figure 4 shown;

[0062] Providing a glass carrier plate 301, the surface of the glass carrier plate 301 is successively coated with a temporary bonding laser reaction layer 302 and a temporary bonding adhesive 303; wherein the thickness of the glass carrier plate 301 is more than 100μm, the thickness of the temporary bonding adhesive 303 is more than 1μm, the thickness of the temporary bonding laser reaction layer 302 is more than 0.1μm, the structure is as follo...

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Abstract

The invention discloses a three-dimensional fan-out wafer level packaging method and packaging structure, and belongs to the field of integrated circuit packaging. The method comprises the steps that firstly, an IC wafer needs to be subjected to seed layer deposition and electroplating processes to form chip copper column protruding blocks, and then the chip copper column protruding blocks are divided into single bare chips; loading by adopting a face up process, and adhering to a pre-designed position of the wafer; lead interconnection in the Z-axis direction is achieved among the multiple layers of chips through mechanical cutting, multiple wiring, copper column protruding blocks, plastic packaging and grinding processes. And finally, carrying out multiple wiring, salient point processing and the like to finish three-dimensional fan-out packaging. According to the invention, lead interconnection in the Z-axis direction is realized through multiple wiring and mechanical cutting modes; the method is simple in technology, short in process, low in preparation cost and suitable for large-scale mass production.

Description

technical field [0001] The invention relates to the technical field of integrated circuit packaging, in particular to a three-dimensional fan-out wafer-level packaging method and packaging structure. Background technique [0002] Three-dimensional stacking technology can effectively shorten the transmission time of signal links, promote the reduction of physical size and weight of components, and create more physical space for system integration. Through breakthroughs in key technologies, the vertical electrical interconnection between chips and circuits is realized in terms of performance, and the signal integrity and frequency characteristics of components are improved while reducing interconnection resistance. At the same time, realizing high-reliability and high-density three-dimensional stacking between devices in structure can increase the wiring density, minimize the dimensions of chips and modules, and maximize the stacking density in the three-dimensional direction,...

Claims

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Application Information

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IPC IPC(8): H01L21/56H01L21/48H01L21/78H01L23/00H01L23/48
CPCH01L21/568H01L21/4825H01L21/78H01L24/11H01L24/14H01L23/481H01L2224/0231H01L2224/02331
Inventor 顾峰光郁澄宇王成迁
Owner 58TH RES INST OF CETC
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