TLB simulator based on SW processor chip architecture and debugging method

Abstract

The invention relates to a TLB simulator based on a SW processor chip architecture, which is characterized in that functional modeling is carried out on a TLB module of a SW high-performance processor chip by using a C + + language to verify the functional correctness of the TLB module; the TLB simulator based on the SW high-performance processor chip architecture comprises an instruction / data virtual-real address conversion module, an instruction / data hit module, an instruction / data refreshing module and an instruction / data filling and replacing module. The instruction / data virtual-real address conversion module is used for receiving an instruction virtual address of an upper-level assembly line and completing virtual-real address substitution by calling the hit, refresh and filling substitution module; the instruction / data hit module judges whether the transmitted virtual address hits the entry storage module or not and sends a result to the filling and replacing module for processing; the instruction / data entry refreshing module is mainly responsible for refreshing effective bits of the entries; and the instruction / data entry filling and replacing module is used for filling and replacing the entries in the entry storage module through a rotation replacement algorithm.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a TLB simulator and a debugging method based on a Shenwei processor chip architecture. Background technique [0002] To speed up the hardware development process designers often use software to model the hardware. When designing a new machine, they usually write an instruction-level simulator or a model of a certain module to test their ideas. These simulators are implemented using hardware description languages ​​and traditional programming languages. Before the actual hardware is implemented, hardware designers can execute programs on these models to verify the performance and accuracy of the hardware design, and take corresponding remedial measures, which greatly reduces the number of rework and improves the speed and quality of hardware development. Contents of the invention [0003] For this reason, the technical problem to be solved by the present inven...

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Problems solved by technology

[0003] For this reason, the technical problem to be solved by the present invention is to overcome the number of times of rework in the development process of accelerated hardware in the prior art and the problem of both speed and quality of hardware development, thereby providing a TLB based on the Shenwei processor chip architecture Simulator and debugging method to find design problems of chip RTL code in time and reduce chip tape-out risk

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