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Parallel equalization method based on FPGA

An equalization method and equalization filter technology, applied in the direction of advanced technology, climate sustainability, sustainable communication technology, etc., can solve problems such as the inability to achieve high-efficiency processing of large data throughput, to increase the maximum clock frequency and improve processing Efficiency, throughput improvement effect

Pending Publication Date: 2022-05-27
HANGZHOU DIANZI UNIV FUYANG ELECTRONIC INFORMATION RES INST CO LTD +1
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Problems solved by technology

The use of traditional horizontal FIR structure filters in FPGA cannot achieve efficient processing of large data throughput

Method used

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  • Parallel equalization method based on FPGA
  • Parallel equalization method based on FPGA
  • Parallel equalization method based on FPGA

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Embodiment 1

[0073] Based on the above-mentioned technical concept of the present invention, in this example, the parallel equalization method based on FPGA specifically includes the following steps:

[0074] Step 1: Generate the local training sequence as a coe file and store it in the ROM in advance. The local training sequence is a pseudorandom sequence (Pseudorandom Sequence) agreed with the transmitter, that is, the preamble part in the frame structure.

[0075] Step 2: The data cache unit is reset, and data 0 is initially cached. Initialize filter tap coefficients.

[0076] Step 3: The received preamble data and the buffered preamble data are simultaneously sent to any filtering unit and tap coefficient updating module, and the preamble data received this time is buffered for use at the next moment.

[0077] Step 4: The y(n) obtained by the filtering unit is sent to the tap coefficient update module, and the tap coefficient update module takes out the corresponding expected signal ...

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Abstract

The invention discloses a parallel equalization method based on an FPGA (Field Programmable Gate Array), which realizes efficient equalization of communication data through an LMS (Least Mean Square) algorithm of which the step length can be dynamically adjusted and by adopting a parallel pipeline filtering structure. The method comprises the following steps: firstly, calculating a tap coefficient of an equalization filter through an LMS algorithm with dynamically adjustable iteration factors; and secondly, through a multi-stage assembly line and multi-path parallel data processing mode, the FPGA data processing efficiency is improved. According to the invention, M paths of data are input into the equalization filter in parallel and M paths of data are output in parallel at the same time in each clock period. Through a parallel and assembly line mode, the data collected by the high-speed ADC can be efficiently equalized by the FPGA.

Description

technical field [0001] The invention relates to the field of signal processing in high-speed communication, in particular to a parallel equalization method based on FPGA, which realizes parallel equalization and efficient processing of communication data through the FPGA. Background technique [0002] Equalization is an important technology in communication systems, not only for analog communication, but also for digital communication. In digital communication and high-speed data transmission systems, in order to overcome inter-symbol interference, reduce the influence of amplitude and delay distortion, and improve the transmission rate as much as possible, channel equalization technology needs to be used. The so-called equalization is to compensate the distortion of the channel. At the same time, due to the time-varying characteristics of channels and interference, in order to achieve efficient data transmission, adaptive technology must be used to automatically adjust sys...

Claims

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Application Information

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IPC IPC(8): H03H17/02
CPCH03H17/0248Y02D30/50G06F30/331G06F12/0855H03H2021/0092H03H2021/0056H03H2220/04G06F12/0884
Inventor 程知群孙庆冉乐超
Owner HANGZHOU DIANZI UNIV FUYANG ELECTRONIC INFORMATION RES INST CO LTD
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