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Flash memory cell with self-aligned gates and fabrication process

A technology of memory cells and gate oxide layers, which is applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., and can solve problems such as short floating gates

Inactive Publication Date: 2007-06-27
SILICON STORAGE TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this method does not require the critical masking step in the formation of the floating gate, it still has the disadvantage of directly performing CMP polishing on the polysilicon or other conductive materials forming the floating gate.
Also, the floating gate is relatively short and provides only limited coupling to the control gate

Method used

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  • Flash memory cell with self-aligned gates and fabrication process
  • Flash memory cell with self-aligned gates and fabrication process
  • Flash memory cell with self-aligned gates and fabrication process

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Experimental program
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Embodiment Construction

[0071] As shown in FIG. 5A , shallow trenches 31 are formed in a silicon substrate 32 . Silicon can be an N-well material, a P-well material, or just a P-type material. A pad oxide 33 is formed on the substrate and a silicon nitride layer 34 is deposited on the pad oxide. These layers are patterned to form a mask, and the substrate is etched through the mask to form trenches.

[0072]An isolation oxide 36 is then deposited in the trench and planarized so that it is flush with the top surface of the nitride layer. The oxide can be deposited by, for example, chemical vapor deposition (CVD) and planarized by CMP polishing. In this method, the pad oxide 33 and the nitride layer 34 not only serve as a mask for forming trenches, but also serve as means for increasing the height of the isolation oxide. As discussed in more detail below, the step height 35 (i.e., the height of the upper surface of the nitride layer on the upper surface of the silicon substrate) is important because...

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Abstract

Nonvolatile memory cell and process in which isolation oxide regions are formed on opposite sides of an active area in a substrate to a height above the substrate on the order of 80 to 160 percent of the width of the active area, a first layer of silicon is deposited on the gate oxide and along the sides of the isolation oxide regions to form a floating gate having a bottom wall which is substantially coextensive with the gate oxide and side walls having a height on the order of 80 to 160 percent of the width of the bottom wall, a dielectric film is formed on the floating gate, and a second layer of silicon is deposited on the dielectric film and patterned to form a control gate.

Description

technical field [0001] The present invention generally relates to semiconductor devices, in particular to a flash memory unit with a self-aligned gate and a manufacturing method thereof. Background technique [0002] Electrically Programmable Read-Only Memory (EPROM) has been widely used as non-volatile memory, which can keep data unchanged even if the power is turned off. However, a major disadvantage of EPROM devices is that they must be exposed to ultraviolet light (UV) for about 20 minutes to erase data. This is inconvenient since the EPROM device must be unplugged from its socket and moved to a UV light source when data needs to be changed. [0003] Electrically Erasable Programmable Read Only Memory (EEPROM) overcomes this problem and allows data to be electrically erased in a much shorter period of time, typically less than 2 seconds. However, it still has the disadvantage of having to erase data byte by byte. [0004] Flash EEPROM is similar to EEPROM in that it c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/788H01L21/336H01L21/28H01L21/8247H01L27/115H01L29/423
CPCH01L27/11521H01L29/42328H01L29/7883H01L29/42324H01L21/28273H01L27/115H01L29/40114H10B69/00H10B41/30
Inventor 陈秋峰
Owner SILICON STORAGE TECHNOLOGY