EEPROM and its mfg. method

Abstract

The present invention provides an electrically-erasable programmable read-only memory. It includes silicon substrate; first oxdie layer formed on the described silicon substrate and second oxide layer whose thickness is greater than that of first oxide layer; polycrystalline silicon floating gate formed on the first oxide layer; oxide / nitride / oxide dielectric layer for covering the described polycrystalline silicon floating gate; polycrystalline silicon control gate formed on the described dielectric layer and used for completely covering described floating gate; and polycrystalline silicon selection gate formed on the described second oxide layer. Said invention also provides a method for making said electrically-erasable programmable read-only memory.

Description

technical field [0001] The present invention generally relates to an electrically erasable programmable read-only memory (EEPROM) and a manufacturing method thereof, and more particularly, to an electrically erasable programmable read-only memory (EEPROM) with a simplified cell structure and smaller cell size Read memory and its manufacturing method. Background technique [0002] Electrically Erasable Programmable Read-Only Memory (EEPROM) is a widely used semiconductor storage device. It has both the readable and writable characteristics of Random Access Memory (RAM) Read memory (ROM) has the advantage of retaining all stored data after power failure. Its biggest advantage is that it can be directly erased by electrical signals, and can also be written by electrical signals. [0003] EEPROM cells usually consist of a select transistor and a memory transistor. The storage transistor includes a stacked gate structure composed of a floating gate and a control gate, the floa...

AI Technical Summary

Problems solved by technology

[0011] There is a disadvantage of the traditional manufacturing process of EEPROM: namely, there is an operation in this manufacturing process to form the tunnel oxide window under the floating gate

The difficulty in defining the second polysilicon layer is due to photoalignment constraints, i.e., sufficient space must be left between the select gate formed by the first polysilicon layer and the control gate formed by the second polysilicon layer. larger

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