Method for providing dopant level for polysilicon for flash memory devices

Abstract

The present invention provides a method and a NAND-type flash memory device. The method includes forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate; forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line high resistance problem and a charge gain / charge loss problem; forming an insulating layer on the doped amorphous silicon layer; forming a control gate layer on the insulating layer; and etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure. In a preferred embodiment, the polysilicon layer which forms both the floating gate of the flash memory cell and the select gate of the select transistor of the device is doped with between approximately 5x1018 and 8x1019 ions / cm3 of phosphorus. With this dopant level, the contact resistance of the select transistor's control gate is low, thus keeping the word line resistivity of the device low. Simultaneously, contamination of the tunnel oxide of the flash memory cell by the dopant is limited, allowing for the interface between the floating gate and the tunnel oxide to be smooth, which prevents charge gain / loss problems. Thus, the reliability of the device is increased.

Description

technical field [0001] The present invention relates to a flash memory device, and more specifically, to a NAND type flash memory device. Background technique [0002] Semiconductor flash memory devices include NAND type flash memory devices. The memory device basically includes a high-density core region and a low-density edge region on a single base. As shown in FIG. 1A and FIG. 1B , the memory cells located in the core area are coupled together in the form of a NAND circuit. FIG. 1A is a schematic circuit diagram of the core area 11 ; and FIG. 1B is a plan view of the core area 11 . Core region 11 contains a memory cell region 22 bounded on one side by drain select transistor portion 24 and on the other side by source select transistor portion 26 . Each select transistor section 24 and 26 includes select gate transistors 24a-24c and 26a-26c, respectively, for selectively activating desired bit lines. [0003] FIG. 1C shows a cross-sectional view of a conventional stac...

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Problems solved by technology

Therefore, it will lead to reliability problems and, when programming and erasing memory cells, charge gain / loss problems

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