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Semiconductor trench device with enhanced gate oxide integrity structure

An oxide layer, silicon oxide technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as being unsuitable for power MOSFETs

Inactive Publication Date: 2003-10-15
GEN SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the method presented here is not suitable for power MOSFETs because the moving arsenic region can cause early avalanche breakdown
And, in the following processes such as sacrificial oxidation treatment and gate oxidation treatment, the part repeatedly doped with arsenic contains silicon defects

Method used

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  • Semiconductor trench device with enhanced gate oxide integrity structure
  • Semiconductor trench device with enhanced gate oxide integrity structure
  • Semiconductor trench device with enhanced gate oxide integrity structure

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Embodiment Construction

[0029] The present invention relates to a trench DMOS device (and also to a method of manufacturing the same) having improved gate oxide integrity, in particular a trench DMOS device having an improved breakdown voltage of the gate oxide layer. These devices and methods of making them are especially useful in making power MOSFET devices.

[0030] figure 2 A first embodiment of a DMOS device made according to the invention is shown. The structure comprises an n+ substrate 3 with a lightly n-doped epitaxial layer 5 thereon. In this doped epitaxial layer, there is a p-type diffusion layer 7 which conducts reversely. The N+ doped epitaxial layer 9 covering at least a part of the p-type diffusion layer functions as a source.

[0031] The first and second trenches 11, 11' are formed in the epitaxial layer. The first trench is placed in the active region 12 of the device and the second trench is placed in the terminal region 12' of the device. The second trench-filled poly...

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PUM

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Abstract

A method for making a trench DMOS (1) is provided that improves the breakdown voltage of the oxide layer in a device having at least a first trench (11) disposed in the active region (12) of the device and a second trench (11') disposed in the termination region (12') of the device. In accordance with the method, mask techniques are used to thicken the oxide layer (13') in the vicinity of the top corner of the second trench, to at least about 1.2 times the thickness of the oxide layer (13) in the first trench, thereby compensating for the thinning of this region (and the accompanying reduction in breakdown voltage) that occurs due to the two-dimensional oxidation during the manufacturing process.

Description

technical field [0001] The present invention relates generally to MOSFET transistors, and more particularly to DMOS transistors having a trench structure. Background technique [0002] A DMOS (Double Diffused MOS) transistor is a type of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that uses diffusion to form the transistor region. DMOS transistors are commonly used in power transistors to provide high voltage circuits for integrated circuits. DMOS transistors can deliver high current per unit area when low forward voltage drop is required. [0003] A typical DMOS circuit consists of two or more single DMOS transistor cells configured in parallel. Individual DMOS transistor cells share a common drain contact (substrate), their sources are shorted together by metal, and their gates are shorted together by polysilicon. Therefore, even though the discrete DMOS circuit is built from a matrix of small transistors, it behaves like a single large transistor. For a...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L21/336H01L29/40H01L29/423H01L29/78
CPCH01L29/66734H01L29/7813H01L29/407H01L29/42368H01L29/7811H01L29/78
Inventor 石甫渊苏根政崔炎曼
Owner GEN SEMICON
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