Method for manufacturing a non-volatile memory device

Abstract

A method for manufacturing a non-volatile memory device which can increase the coupling ratio and can avoid affecting the height of a control gate by forming a trench in a cell region and forming a floating gate in a concave shape in the trench is disclosed. The method comprises: forming a first trench having a first depth on a silicon substrate of a peripheral circuit region, burying the same with a buried oxide film and planarizing the same; forming a second trench having a second depth on the silicon substrate of the cell region; carrying out channel ion implantation to the cell region, forming a tunnel oxide film in the second trench and depositing a floating gate material; forming a floating gate by etching the floating gate material; forming a source / drain junction in the cell region; forming wells in the peripheral circuit and cell regions and depositing a dielectric film; depositing a gate material while leaving the dielectric film only in the channel portion of the cell region; and forming a gate in the peripheral circuit region and a control gate in the cell region by etching the gate material.

Description

technical field [0001] The present invention relates to a method of manufacturing a non-volatile memory device, in particular to a method of forming a trench in a cell region, forming a concave floating gate in the trench, and forming a dielectric film to cover the floating gate. To avoid affecting the control gate height of the non-volatile memory device manufacturing method. Background technique [0002] Non-volatile memory devices can retain their previous data even if their power supply is cut off. These nonvolatile memory devices include electrically programmable read-only memory (EPROM) that can be programmed electrically and erased by exposure to ultraviolet light and electrically erasable read-only memory (EEPROM) that can be programmed and erased electrically. Among EEPROMs, flash memory has a small chip size and excellent programming and erasing characteristics. [0003] Non-volatile memory devices generally include a floating gate, which is capable of accumulati...

AI Technical Summary

Problems solved by technology

Therefore, it is difficult to increase the capacitance by increasing the area of ​​the floating gate

[0009] In particular, as the height of the floating gate in SoC products that store EEPROM cells has become larger, the height of the control gate has also become larger, creating a problem that it is difficult to pattern the logic of peripheral circuits at the same time grid and control grid

In addition, as the distance between the bit line contact and the control gate in the EEPROM cell becomes shorter, this can cause an electrical short, exceeding the required predetermined gap, and thereby increasing the cell size

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