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3D polysilicon read only memory and preparation method

A technology of read-only memory and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., and can solve problems such as the influence of the correct position of memory cells and the impact on product qualification rate

Active Publication Date: 2005-06-15
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, since the region where the electrical breakdown occurs is arbitrary, there is no limited region that can be defined on the interface between the two polysilicon layers, so that the correct position of the memory cell is affected and affects the quality of the product. Pass rate

Method used

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  • 3D polysilicon read only memory and preparation method
  • 3D polysilicon read only memory and preparation method
  • 3D polysilicon read only memory and preparation method

Examples

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no. 1 example

[0018] Please refer to Figure 2A , Figure 2A Shown is a cross-sectional view of the three-dimensional polysilicon ROM according to the first embodiment of the present invention. The three-dimensional polysilicon ROM 20 includes: a silicon substrate 210 , an insulating oxide layer 211 , an N-type heavily doped polysilicon layer 220 , a P-type lightly doped polysilicon layer 240 , a dielectric layer 230 , and oxide layers 224 and 244 .

[0019] The insulating oxide layer 211 is located on the silicon substrate 210 , and the N-type heavily doped polysilicon layer 220 is located on the insulating oxide layer 211 . The N-type heavily doped polysilicon layer 220 is located on the silicon substrate 210, and the N-type heavily doped polysilicon layer 220 includes several mutually spaced and parallel word lines (Word Line, WL), for the convenience of description, in Figure 2A , represented by three word lines, which are respectively word lines 222a, 222b, and 222c. The oxide laye...

no. 2 example

[0027] Please also refer to Figure 3A, Figure 3B-3F , FIG. 3A shows a flowchart of a method for manufacturing a three-dimensional polysilicon read-only memory according to a second embodiment of the present invention, and Figure 3B-3F Shown is a cross-sectional view of the process of the manufacturing method of the three-dimensional polysilicon read-only memory according to the second embodiment of the present invention. Such as Figure 3F As shown, the three-dimensional polysilicon ROM 30 includes a silicon substrate 310 , an insulating oxide layer 311 , an N-type heavily doped polysilicon layer 320 , a dielectric layer 330 , a P-type lightly doped polysilicon layer 340 , 350 and an oxide layer 344 , 354 .

[0028] The manufacturing method of the 3D polysilicon ROM according to the second embodiment of the present invention is as follows: First, in step 361 , a silicon substrate 310 is provided. Next, in step 363 , an insulating oxide layer 311 is deposited on the substra...

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Abstract

3D polysilicon read only memory includes silicon base plate, insulation oxide layer, N type heavily doped polycrystalline silicon layer, P type light doped polycrystalline silicon layer, dielectric layer and dioxide layer. Insulation oxide layer is on silicon base plate. N type heavily doped polycrystalline silicon layer on insulation oxide layer includes several separated word lines parallel to each other. There is an oxide layer between word lines, and dielectric layer is located on word lines and oxide layer. P type light doped polycrystalline silicon layer on dielectric layer includes several separated bit lines parallel to each other. Bit line is perpendicular to word line, but they are interlaced. A neck structure in dielectric layer is formed under word lines. Another oxide layer positioned between bit lines is located on word lines and first oxide layer.

Description

【Technical field】 [0001] The present invention relates to a read-only memory and its manufacturing method, and in particular to a three-dimensional polysilicon read-only memory and its manufacturing method. 【Background technique】 [0002] Non-volatile memory has the function of "memory". Even after the power is turned off, the data stored in the IC can still be saved. Generally speaking, non-volatile memory can be roughly divided into mask read-only memory (MASKROM), one-time programmable read-only memory (OTP ROM), erasable and programmable read-only memory (EPROM), electrically erasable And programmable read-only memory (EEPROM), flash memory (Flash Memory) and multiple times programmable read-only memory (MTP ROM), etc. In the OTP memory array, a fuse is installed on the connecting wire between the transistor and the transistor. When the customer uses the programmer to blow the fuse that is not needed by the OTP to store the program, because the destruction of the fuse ...

Claims

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Application Information

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IPC IPC(8): H01L21/8246H01L27/112
Inventor 徐子轩李明修龙翔澜吴昭谊
Owner MACRONIX INT CO LTD
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