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Production of non-volatile memory

A non-volatile, manufacturing method technology, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems that affect the stability of components and reduce the performance of components, so as to increase conductivity and reduce gate Resistor, the effect of saving manufacturing cost

Active Publication Date: 2006-11-01
POWERCHIP SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the resistance of the doped polysilicon is much higher than that of the metal silicide, the electrical operation of the storage unit 102 and the storage unit 116 will obviously have a gap, thereby reducing the performance of the device and affecting the stability of the device.

Method used

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  • Production of non-volatile memory
  • Production of non-volatile memory
  • Production of non-volatile memory

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Experimental program
Comparison scheme
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Embodiment Construction

[0041] 2A to 2G The drawing is a cross-sectional view of a manufacturing process of a non-volatile memory according to a preferred embodiment of the present invention.

[0042] Please refer to Figure 2AFirst, a substrate 200 is provided, and a plurality of storage cells 207 are formed on the substrate 200, and each storage cell 207 has a gap 208 between each other. The memory cell 207 is composed of, for example, a composite dielectric layer 201 , a gate electrode 203 and a cap layer 205 . The formation method of the memory cell 207 is, for example, after sequentially forming a composite dielectric material layer, a gate material layer, and an insulating material layer on the substrate 100 , and then patterning the above material layers by photolithography and etching technology.

[0043] The composite dielectric layer 201 is, for example, composed of a bottom dielectric layer 201a, a charge trapping layer 201b, and a top dielectric layer 201c. The material of the bottom ...

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PUM

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Abstract

The process provided for fabricating a NVRAM (non-volatile random access memory) comprises: providing a substrate; forming multi first memory cells on the said substrate; there is a gap between each two spacers; forming an insulation spacer on the sidewall of each memory cell; forming a composite electric layer on said substrate; forming a doping poly crystalline silicon layer to fill out the gaps between memory cells; removing a portion of said doping crystalline silicon layer to form multi trenches; forming a metal layer on substrate to fill out the trenches; removing a portion of metal layer to form the gate electrode; the gate electrode and the composite dielectric layer composes the second memory cells; the second storage cell and the first storage cell composes a memory cell array structure; forming the source region and drain region on substrate aside said memory cell area structure.

Description

technical field [0001] The present invention relates to a method for manufacturing a semiconductor memory element, in particular to a method for manufacturing a non-volatile memory. Background technique [0002] Among various non-volatile memory products, it has the advantage that data can be stored, read, and erased for many times, and the stored data will not disappear after the power is turned off. Program read-only memory (EEPROM) has become a memory element widely used in personal computers and electronic equipment. [0003] A typical EEPROM is made of doped polysilicon for floating gates and control gates. In the prior art, a charge trapping layer is also used to replace the polysilicon floating gate, and the material of the charge trapping layer is silicon nitride, for example. This silicon nitride charge trapping layer usually has a layer of silicon oxide above and below it, and forms a silicon oxide / silicon nitride / silicon oxide (oxide-nitride-oxide, ONO for short...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H10B69/00
Inventor 朱建隆毕嘉慧魏鸿基曾维中
Owner POWERCHIP SEMICON MFG CORP