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Semiconductor nano-wire, and semiconductor device provided with that nano-wire

A technology of nanowires and semiconductors, applied in semiconductor devices, semiconductor/solid-state device manufacturing, nanotechnology, etc., can solve the problems of small contact area between nanowires and source/drain electrodes, plastic substrates are not resistant to heat treatment to reduce contact resistance, etc. , achieve the effect of simplifying the manufacturing process, low contact resistance, and suppressing the deviation of mask alignment

Inactive Publication Date: 2007-02-28
JOLED INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] Furthermore, the contact area of ​​the nanowires with the source / drain electrodes is small, and there is also the problem that the plastic substrate is not resistant to the heat treatment required to reduce the contact resistance

Method used

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  • Semiconductor nano-wire, and semiconductor device provided with that nano-wire
  • Semiconductor nano-wire, and semiconductor device provided with that nano-wire
  • Semiconductor nano-wire, and semiconductor device provided with that nano-wire

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Embodiment approach 1

[0061] Hereinafter, a first embodiment of the nanowire of the present invention will be described with reference to FIGS. 1 and 2 . FIG. 1 is a perspective view of a nanowire 100 in this embodiment. 2( a ) is a cross-sectional view along the long axis direction of the nanowire 100 , and FIG. 2( b ) is a cross-sectional view of a field effect transistor including the nanowire 100 .

[0062] The nanowire 100 shown in FIGS. 1 and 2 has: a pair of contact regions 10a, 10b; and a channel region 12 connected to these contact regions 10a, 10b. In the present embodiment, the channel region 12 is formed of silicon (Si), but the contact regions 10a and 10b have conductive portions formed of a material different from Si at least on the surface. More specifically, the contact regions 10a, 10b are configured to include: a core portion made of Ge doped with a p-type impurity at a high concentration; and an alloy portion (here, The channel region of the p-type semiconductor is described, b...

Embodiment approach 2

[0107] Next, a second embodiment of the present invention will be described with reference to FIGS. 9( a ) and ( b ).

[0108] FIG. 9( a ) is a diagram showing a nanowire according to this embodiment, and FIG. 9( b ) is a plan view of a field effect transistor manufactured using such a nanowire.

[0109] The feature of this embodiment is that, as shown in Figure 9(a), a nanowire includes more than three contact regions 10 1 ~10 N (N is an integer greater than or equal to 3), two or more channel regions 12 1 ~12 M (M is an integer of 2 or more).

[0110] Such a nanowire can be produced by repeatedly performing the crystal growth process described with reference to FIGS. 5( b ) to ( d ), for example, by alternately growing Ge portions and Si portions. In this case, in that only the Si portion is covered with an insulating film and the surface of the Ge portion is selectively alloyed, it is different from the above-mentioned

[0111] The implementation is the same.

[0112]...

Embodiment approach 3

[0126] Next, a third embodiment of the present invention will be described with reference to FIG. 11 .

[0127] FIG. 11 is a plan view of a field effect transistor produced using the nanowire 200 of this embodiment. The difference from the field effect transistor shown in FIG. 6 is that the length of the channel region of the nanowire 200 is shorter than the distance between the source electrode 16a and the drain electrode 16b.

[0128] In this embodiment mode, the channel length is shortened beyond the limit of photolithography technology. As mentioned above, the channel length is defined as the length of the channel region of the nanowire, which can be controlled by the growth process of the nanowire. Therefore, the length of the channel region can be set to an extremely short value (for example, in the range of 50 to 1000 nm, preferably 500 nm or less), regardless of the limit of photolithography technology.

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Abstract

A nano-wire (100) comprising a plurality of contact regions (10a, 10b) and at least one channel region (12) connected with the plurality of contact regions (10a, 10b), wherein the channel region (12) is formed of a first semiconductor material, the surface of the channel region (12) is covered with an insulation layer selectively formed on the channel region (12), each of the plurality of contact regions (10a, 10b) is formed of a second semiconductor material different from the first semiconductor material of the channel region (12), and at least the surface of the channel region (12) has a conductive portion.

Description

technical field [0001] The present invention relates to semiconductor nanowires, and more particularly to semiconductor nanowires having a novel configuration suitable for achieving low contact resistance, and semiconductor devices including the semiconductor nanowires. Background technique [0002] In the field of nanotechnology, research into wires (nanowires) or tubes (nanotubes) having diameters on the order of nanometers is actively developing. In particular, attention has been paid to transistors using semiconductor nanowires formed by self-organization in their channel regions. Semiconductor nanowires are grown on the substrate by, for example, a VLS mechanism after forming metal fine particles functioning as catalysts for crystal growth on the substrate (Patent Document 1, etc.). Therefore, when integrating a practical transistor circuit on a substrate, it is necessary to grow semiconductor nanowires at target positions. [0003] On the other hand, it is reported t...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L29/786H01L29/06
CPCH01L29/78618H01L29/78696H01L29/78684H01L29/775H01L27/1214H01L29/7869B82Y10/00H01L29/0665H01L29/78681H01L29/0673Y10S977/762Y10S977/938
Inventor 斋藤彻川岛孝启
Owner JOLED INC
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