Method of improving moisture resistance of low dielectric constant films

Abstract

A method and apparatus for depositing a low dielectric constant film includes depositing a silicon oxide based film, preferably by reaction of an organosilicon compound and an oxidizing gas at a low RF power level from about 10W to about 500W, exposing the silicon oxide based film to water or a hydrophobic-imparting surfactant such as hexamethyldisilazane, and curing the silicon oxide based film at an elevated temperature. Dissociation of the oxidizing gas can be increased in a separate microwave chamber to assist in controlling the carbon content of the deposited film. The moisture resistance of the silicon oxide based films is enhanced.

Description

BACKGROUND OF THE DISCLOSURE[0001] 1. Field of the Invention[0002] The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a process and apparatus for treating dielectric layers deposited on a substrate.[0003] 2. Background of the Invention[0004] One of the primary steps in the fabrication of modem semiconductor devices is the formation of metal and dielectric films on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed on the substrate. A preferred method of depositing metal and dielectric films at relatively low temperatures is plasma-enhanced CVD (PECVD) techniques such a...

AI Technical Summary

Problems solved by technology

The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed on the substrate.

However, the barrier / liner layers typically have dielectric constants that are significantly greater than 4.0, and the high dielectric constants result in a combined insulator that does not significantly reduce the dielectric constant.

Furthermore, known low k dielectric materials generally have low oxide content which makes the material inadequate as an etch stop layer during etching of vias and / or interconnects.

This may lead to crosstalk and / or resistance-capacitance (RC) delay that degrades the overall performance of the device.

Images