Apparatus and method for argon plasma induced ultraviolet light curing step for increasing silicon-containing photoresist selectivity

Abstract

Provided is a method and apparatus for increasing an etching selectivity of photoresist material. An exemplary method initiates with providing a substrate with a developed photoresist layer. The developed photoresist layer on the substrate includes polymer chains containing silicon. Next, the substrate and developed photoresist layer are exposed to an ultraviolet (UV) light, where the UV light emanates from a UV generating agent. A portion of the developed photoresist layer is then converted to a hardened layer where the hardened layer is created by cross-linking the polymer chains containing silicon and the cross-linking is activated by the UV light. Next an etch may be performed on the substrate using the hardened layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional to copending prior U.S. patent application Ser. No. 09 / 894,230, filed Jun. 27, 2001, and entitled “APPARATUS AND METHOD FOR ARGON PLASMA INDUCED ULTRAVIOLET LIGHT CURING STEP OR INCREASING SILICON-CONTAINING PHOTORESIST SELECTIVITY.” This application is incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates generally to lithography and more particularly to a method and apparatus for increasing the selectivity of a silicon-containing photoresist layer to improve profile control of etched features without decreasing wafer throughput. [0004] 2. Description of the Related Art [0005] The ability to work selectively on small well defined areas of a substrate is paramount in the manufacture of semiconductor devices. In the continuing quest to achieve higher levels of performance and higher functional density of the semiconductor devices, the m...

AI Technical Summary

Benefits of technology

The hardened layer enhances etch selectivity, enabling pinpoint accuracy in semiconductor feature sizes, improving etch profile control, and increasing wafer throughput by allowing etching to occur in the same chamber without removing the wafer, thus maintaining high density and performance.

Problems solved by technology

Sharp lithographic transmission becomes more of a challenge as wafers progress to higher density chips with shrinking geometries.

Furthermore, as metallization transitions to dual damascene processes, lithography techniques to pattern holes or trenches in the dielectric become more critical.

Moreover, as device features progressively become smaller, the aspect ratios for those same features become greater, thereby making it more difficult to accurately perform etching operations.

However, resist compositions containing silicon, either in the main resist polymer or by post-exposure surface treatment (e.g., silylation), have either failed to deliver adequate improvement in etch resistance or have had poor processing performance due to the unacceptable selectivity past the silicon containing layer.

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