Method of manufacturing semiconductor device

Abstract

Disclosed herein is a method for manufacturing a semiconductor device, the method including the steps of: forming a recess in an insulating film provided over a substrate; forming a plating seed layer in such a way that an inner wall of the recess is covered, the plating seed layer arising from sequential deposition of an alloy layer composed of copper and a metal other than copper and a conductive layer composed mainly of copper; burying a conductive layer composed mainly of copper by plating in the recess on which the plating seed layer is provided; and carrying out heat treatment to cause the metal in the alloy layer to react with a constituent in the insulating film, to thereby form a barrier film composed of a metal compound having a copper diffusion barrier function at an interface between the alloy layer and the insulating film.

Description

CROSS REFERENCES TO RELATED APPLICATIONS[0001]The present invention contains subject matter related to Japanese Patent Application JP 2006-222194 filed in the Japan Patent Office on Aug. 17, 2006, the entire contents of which being incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that has a damascene structure in which a self-formed barrier film is provided between an interconnect or via and an interlayer insulating film.[0004]2. Description of the Related Art[0005]In a general process for forming a copper (Cu) interconnect in a semiconductor device, a damascene method is employed, in which an interconnect pattern is formed by filling an interconnect trench provided in an interlayer insulating film. In formation of a Cu interconnect by use of the damascene method, generally before bur...

AI Technical Summary

Benefits of technology

[0014]There is a need for the present invention to provide a method for manufacturing a semiconductor device, allowing prevention of separation of a conductive layer while suppressing the burden on a plating step, and allowing enhancement in the uniformity of the coverage of the conductive layer across the substrate plane while suppressing increase in the interconnect resistance.

[0016]According to such a method for manufacturing a semiconductor device, even when the resistance of the metal other than Cu contained in the alloy layer is high, the sheet resistance of the plating seed layer is lower than that of a plating seed layer formed only of the alloy layer, because the plating seed layer arising from sequential deposition of the alloy layer and the conductive layer composed mainly of Cu is formed. Therefore, even when the concentration of the metal in the alloy layer is increased to such an extent that a continuous barrier film is formed, increase in the sheet resistance of the plating seed layer is suppressed. This eliminates the need to apply a large current in a plating step, and thus suppresses the burden on the plating step. Thus, with the burden on the plating step suppressed, a continuous barrier film can be formed at the interface between the alloy layer and the insulating film by increasing the concentration of the metal in the alloy layer. This enhances the adhesiveness between the conductive layer and the insulating film, which can prevent separation of the conductive layer. In addition, due to the low sheet resistance of the plating seed layer, unevenness of the plating growth of the conductive layer across the substrate plane is suppressed and the uniformity of the coverage of the conductive layer is enhanced. Moreover, because the alloy layer in the plating seed layer is covered by the conductive layer composed mainly of Cu, the metal on the surface side of the alloy metal is prevented from being eluted in a plating solution in the plating step. This prevents increase in the resistance of the conductive layer due to burying of the metal eluted in the plating solution in the recess together with the conductive layer at the time of filling of the recess with the conductive layer by plating.

[0017]As described above, the method for manufacturing a semiconductor device according to an embodiment of the present invention can prevent separation of a conductive layer, and thus can enhance the yield of the semiconductor device. Furthermore, the uniformity of the coverage of the conductive layer across the substrate plane is enhanced, which can suppress dishing and erosion that will occur in polishing of the conductive layer by e.g. CMP. Moreover, increase in the resistance of the conductive layer can be prevented. Consequently, when the recess is an interconnect trench and the conductive layer is an interconnect, increase in the interconnect resistance can be prevented and the interconnect reliability can be enhanced.

Problems solved by technology

However, the above-described manufacturing method involves the following problems.

This leads to the necessity for application of a large current in the plating step, and thus increases the burden on the plating step.

This causes unevenness of the plating growth of the conductive layer 18 across the plane of the substrate 11, which results in low uniformity of the coverage of the conductive layer 18.

Moreover, Mn on the surface side of the plating seed layer 17′ is easily eluted in a plating solution, which leads to a problem that the Mn eluted in the plating solution is buried in the interconnect trench 16 together with the conductive layer 18 and hence the interconnect resistance increases.

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