Multipath Soldered Thermal Interface Between a Chip and its Heat Sink

Abstract

The invention comprises a process for joining a first surface and a second surface where the first surface comprises an initially non-solderable surface which comprises coating the first surface with a solder-adhesion layer to produce a solder-adhesion layer on the first surface and providing a Thermal Interface Material (“TIM”) composition comprising solderable heat-conducting particles in a bondable resin matrix where at least some of the solderable heat-conducting particles comprise a solder surface. The TIM composition is placed between the first surface and the second surface to extend between and be contiguous with both the second surface and the solder-adhesion layer on the first surface. Sufficiently heating the TIM composition results in (a) soldering at least some of the solderable heat-conducting particles to one another; and (b) soldering at least some of the solderable heat-conducting particles to the solder-adhesion layer on the first surface. When the second surface comprises a solderable surface, the particles will also bond to it. When the second surface is not solderable, a solder adhesion layer can be placed on it. The process also includes adhesively bonding the resin matrix to the first surface and the second surface. The first surface can comprise an electronic device such as a semiconductor device and the second surface can comprise a heat sink, such as a solderable heat sink. The invention also comprises a process for improving the heat conductivity of a TIM, an article of manufacture made by the process, and a composition of matter comprising the TIM.

Description

FIELD OF THE INVENTION[0001]The filed of the invention in one aspect comprises a thermal interface material (“TIM”) employed in reducing the thermal resistance between an electronic device and a heat sink.RELATED ART[0002]The so-called “silicon revolution” brought about the development of faster and larger computers beginning in the early 1960's with predictions of rapid growth because of the increasing numbers of transistors packed into integrated circuits, and estimates they would double every two years. Since 1975, however, they doubled about every 18 months.[0003]An active period of innovation in the 1970's followed in the areas of circuit design, chip architecture, design aids, processes, tools, testing, manufacturing architecture, and manufacturing discipline. The combination of these disciplines brought about the VLSI era and the ability to mass-produce chips with 100,000 transistors per chip at the end of the 1980's, succeeding the large scale Integration (“LSI”) era of the ...

AI Technical Summary

Benefits of technology

The present invention provides a thermal interface material (TIM) with reduced thermal resistance to improve cooling of electronic devices such as semiconductor chips. The TIM comprises solderabte heat-conducting particles in a bondable resin matrix positioned between the chip and a heat exchange surface. The solderable heat-conducting particles bond to the surfaces upon heating, forming multiple heat conduction paths. The TIM avoids a completely solid solder layer between the chip and the heat sink, and provides a multipath solderable interface that addresses any problem due to a thermal coefficient of expansion mismatch between the surfaces when exposed to elevated temperatures. The technical effects of the invention include improved cooling of electronic devices and reduced thermal resistance.

Problems solved by technology

Chen, U.S. Pat. No. 6,951,001, notes that continued scaling of the complementary metal oxide semiconductor (“CMOS”) fabrication process increases the number of devices on a VLSI chip but causes “within-die” variations that can become significant problems such as Le (the effective channel Length) and Vt (threshold voltage) as well as supply voltage and temperature variations.

Within-die variations can also cause on-chip signal timing uncertainties.

This approach often leads to “over designing,” which may cause increasingly high power requirements and reliability problems.

High power requirements can lead to overheating.

While smaller chip geometries result in higher levels of on-chip integration and performance, higher current and power densities, increased leakage currents, and low-k dielectrics with poorer heat conductivity occur that present new challenges to package and heat dissipation designs.

This increase in power density also increases the operating temperature of the device.

Addressing the resultant thermal resistance between the backside of a chip and a heat sink using current thermal greases is at best 4.5 W / m K, not adequate to cool the chips.

Loading thermally conducting particles such as copper, silver, carbon nanotubes or other materials into a thermal grease lowers its inherent thermal resistance, however, a common problem of this approach lies in effecting thermal conduction between the particles via proximity of the particles to one another.

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