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Protecting integrity of data in multi-layered memory with data redundancy

Inactive Publication Date: 2010-06-24
III HLDG 1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Regardless, in a HDD a head media failure (“head crash”), once it occurs, is a catastrophic failure that is usually irrecoverable.
However, using flash memory has a few drawbacks.
Second, additional circuitry is required to implement the erase operation.
The additional circuitry increases die area and the cost per bit.
Third, flash memory usually requires additional file management software that must be mapped on top of the standard file management structure in order to perform the erase operation (e.g., a block erase operation).

Method used

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  • Protecting integrity of data in multi-layered memory with data redundancy
  • Protecting integrity of data in multi-layered memory with data redundancy
  • Protecting integrity of data in multi-layered memory with data redundancy

Examples

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Embodiment Construction

[0027]U.S. patent application Ser. No. 11 / 095,026, filed Mar. 30, 2005, entitled “Memory Using Mixed Valence Conductive Oxides,” and published as U.S. Pub. No. US 2006 / 0171200 A1 on Aug. 3, 2006, is herein incorporated by reference in its entirety and for all purposes, and describes non-volatile third dimensional memory elements that may be arranged in a two-terminal, cross-point memory array. The memory elements can be a component of a memory cell that includes electrically in series with the memory element, other structures including but not limited to a non-ohmic device (NOD) and electrodes. New non-volatile memory structures are possible with the capability of this third dimensional memory array. The technology allows for the emulation of other memory technologies by duplicating the interface signals and protocols, while accessing the third dimensional memory array. The third dimensional memory array may emulate other types of memory (e.g., DRAM, SRAM, FLASH, and ROM), providing...

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PUM

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Abstract

Systems, integrated circuits, and methods for protecting data stored in third dimensional vertically stacked memory technology are disclosed. An integrated circuit is configured to perform duplication of data disposed in multi-layered memory that can comprise two-terminal cross-point memory arrays fabricated BEOL on top of a FEOL logic layer that includes active circuitry for performing data operations (e.g., read, write, program, and erase) on the multi-layered memory. For example, the integrated circuit can include a first subset of BEOL memory layers configured to store data, a second subset of the BEOL memory layers configured to store a copy of the data from the first subset of memory layers, a FEOL redundancy circuit coupled to the first subset of the memory layers and the second subset of the memory layers, the redundancy circuit being configured to provide both a portion of the data and a copy of the portion of the data.

Description

FIELD OF THE INVENTION[0001]Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for multi-layered memory protection with data redundancy implementing, for example, third dimensional memory technology.BACKGROUND OF THE INVENTION[0002]Traditional storage technologies, such as hard disk drive technologies (HDD), have used memory protection techniques to preserve file directories and access pointer systems, including file allocation tables (FATs) such as the kind used in a computer software operating system, such as the Disk Operating Systems (DOS), for example. Those pointers, directories, and tables are very valuable data which might be lost in the event of a system failure. In that some data is more important than other data, it is important to protect important data in the event of a system failure, a HDD crash, or the like. In some applications, user data is also important and needs to...

Claims

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Application Information

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IPC IPC(8): G06F11/20G06F11/00
CPCH03M7/30G11C5/02
Inventor NORMAN, ROBERT
Owner III HLDG 1
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