Disturb-Free Static Random Access Memory Cell

Abstract

A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority, under 35 U.S.C. §119(e), of Provisional Application No. 61 / 365,165, filed Jul. 16, 2010, incorporated herein by this reference.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT[0002]Not applicable.BACKGROUND OF THE INVENTION[0003]This invention is in the field of solid-state memory. Embodiments of this invention are more specifically directed to static random access memory (SRAM) cells and devices.[0004]Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing t...

AI Technical Summary

Benefits of technology

[0025]Embodiments of this invention provide a memory cell, and method of operating the same, in which cell stability is improved and disturb vulnerability is eliminated without impacting write margin.

[0026]Embodiments of this invention provide such an array and method in which design constraints on the memory cells can be skewed to favor write margin without sacrificing cell stability.

Problems solved by technology

However, this physical scaling of device sizes raises significant issues, especially in connection with embedded SRAM and in SRAM realized as “stand-alone” memory integrated circuit devices.

Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes.

This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis.

The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written as expected.

As mentioned above, device variability can cause read and write failures, particularly in memory cells constructed with sub-micron minimum feature size transistors.

A write failure occurs when an addressed SRAM cell does not change its stored state when written with the opposite data state.

Typically, this failure has been observed to be due to the inability of write circuitry to pull down the storage node currently latched to a high voltage.

Cell stability failures are the converse of write failures—a write failure occurs if a cell is too stubborn in changing its state, while a cell stability failure occurs if a cell changes its state too easily.

However, both the conventional 6-T cell of FIG. 1a and the conventional 8-T cell of FIG. 1b are vulnerable to unintentional change of state during the writing of data to other cells.

More specifically, it has been observed that SRAM cells in unselected columns of selected rows (i.e., “half-selected” cells) are especially vulnerable to the “disturb” condition present on their bit lines during writes to cells in the same row.

This effect can upset the stored data state, particularly for half-selected cells in which the transistors are imbalanced due to process variations.

In addition, noise of sufficient magnitude coupling to the bit lines of the half-selected columns, during a write to the selected columns in the same row, can cause a false write of data to those half-selected columns.

The possibility of such stability failure is exacerbated by device mismatch and variability, as discussed above.

Unfortunately, the design window in which both adequate cell stability and adequate write margin can be attained is becoming smaller with continued scaling-down of device feature sizes, for the reasons mentioned above.

In addition, it has been observed that the relative drive capability of p-channel MOS transistors relative to re-channel MOS transistors is increasing as device feature sizes continue to shrink, which skews the design window toward cell stability over write margin.

However, because pass transistors 15a, 15b are turned on for unselected columns in selected row j, cell 12″j,k also suffers from the cell stability, or disturb vulnerability, described above.

The isolation gate, when turned off, eliminates modulation at one of the storage nodes from affecting the state of the opposite inverter, breaking the feedback loop for bit line noise and inhibiting stability failures.

In addition, the asymmetric layout of the 7-T cell precludes implementation in an interleaved array architecture, increasing the likelihood of multiple-bit soft errors, and further reducing chip area efficiency.

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