Redundancy for on-chip interconnect

Abstract

One embodiment sets forth a technique for on-chip satisfying timing requirements of on-chip source-synchronous, CMOS-repeater-based interconnect. Each channel of the on-chip interconnect may include one or more redundant wires. Calibration logic is configured to apply transition patterns to wires comprising each channel and calibration patterns that are generated in response to the transition patterns are captured. Based on the calibration patterns, wires that best satisfy the timing requirements of the on-chip interconnect are selected for use to transmit data. The calibration logic also trims the delays of the clock and selected data wires based on captured calibration patterns to improve the timing margin of the on-chip interconnect. Improving the timing margin of the on-chip interconnect improves chip yields.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to on-chip interconnect and more specifically to redundancy to satisfy on-chip interconnect timing.[0003]2. Description of the Related Art[0004]A source-synchronous, complementary metal-oxide-semiconductor (CMOS)-repeater-based interconnect provides a simple, high-performance topology for global on-chip communication fabrics. However as silicon die sizes increase, the on-chip interconnect may span 10 mm or more in length and the communication channels are subject to many sources of timing error including crosstalk, power-supply-induced jitter (PSIJ), and wire delay variation due to transistor and wire metallization mismatch.[0005]For a 10-mm lower-level metal wire with 130 um width and space, 50% utilization on adjacent layers, and with repeater size and spacing optimized for the minimum power-delay product, the 1-σ delay variation is about 8 ps per transition polarity per wire du...

AI Technical Summary

Benefits of technology

This patent describes a way to make sure that data can be transmitted through an on-chip network using CMOS repeaters. The system uses calibration logic to make sure that the timing requirements are met and the best wires are used for data transmission. This helps improve the reliability of the network and increases the yield of good chips.

Problems solved by technology

However as silicon die sizes increase, the on-chip interconnect may span 10 mm or more in length and the communication channels are subject to many sources of timing error including crosstalk, power-supply-induced jitter (PSIJ), and wire delay variation due to transistor and wire metallization mismatch.

Power supply noise on the order of + / −7% can result in significant modulation of data rate (through modulation of signal propagation velocity), further reducing the effective timing margin by as much as 400 mUI.

In such harsh environments, wire delay mismatch can cause chips to fail to operate properly, as explained above regarding the transmission of the “lone 1”, resulting in severe yield loss.

The combination of wire delay mismatches, timing jitter, and power supply noise may reduce the effective timing margin such that clock frequency must be reduced to ensure that timing margin constraints are met so that the chip operates properly.

In particular, the chips may fail when an on-chip source-synchronous, CMOS-repeater-based interconnect serves as the building block for large on-chip networks responsible for moving several terabytes of data per second across large portions of the chip.

Failure of even a single signal transmitted on the wire of the interconnect to satisfy the timing requirements will likely result in a functional failure of the chip.

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