Computing method for meal gate surface appearance

Abstract

The invention discloses a computing method for metal gate surface appearance and belongs to the technical field of integrated circuit manufacturing and electronic design automation. The method includes acquiring map information and measure parameter information of the metal gate surface appearance, then establishing a parameter prediction model of the metal gate surface appearance, and performing a prediction for the surface appearance on the back of a designed metal gate structure corrugated metal pipe (CMP) in a chip design process through the prediction model to obtain dish-shaped appearance of the metal gate and erosion appearance of dielectrics among metal gates. Accordingly, area which is probable to generate problems after the CMP processing step in the design can be found out, the area is provided for designers to improve, the corresponding problems occurring in the manufacturing process are avoided, and thereby the yield of products is improved.

Description

technical field [0001] The invention relates to the technical fields of integrated circuit manufacturing and electronic design automation, in particular to a calculation method for the surface topography of a metal grid. Background technique [0002] As the integrated circuit manufacturing process node enters 32nm and below, the traditional CMOS (Complementary Metal Oxide Semiconductor) device size reduction technology path faces a technical bottleneck: on the one hand, the ever-decreasing thickness of the gate oxide layer leads to increasing leakage current, The power consumption of the device is increased, and the performance and reliability of the device are reduced; on the other hand, the thickness of the gate oxide layer is also close to the limit, and the gate oxide layer with only a few layers of silicon atomic thickness is facing a situation where there will be no silicon available if it continues to thin. In order to ensure that the performance is improved while the...

AI Technical Summary

Problems solved by technology

The result of the metal gate CMP process step has a great impact on the subsequent process. Excessive polishing will cause damage to the source and drain regions during contact etching, while insufficient polishing will cause short circuits between devices. Both will make the integrated circuit chip unable to work. , affecting chip yield

[0004] At the same time, in the metal gate CMP step of the high-k / metal gate device structure, different gate lengths, gate widths, and gate-to-gate spacings will affect the surface morphology after CMP, and at the same time produce metal dishing and dielectric erosion, etc. defect

In addition, in the complex integrated circuit design, although strict design rules have been restricted, the geometric parameters of the gate can still be changed within a certain range, thus affecting the surface morphology of the silicon wafer after CMP in the manufacturing process, making the Different positions of the chip have different heights, which will adversely affect the subsequent process steps such as photolithography and etching, thus affecting the chip yield

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