Metal-insulator-metal capacitor and methods of fabrication

Abstract

A method of forming a semiconductor structure, comprising forming a dual damascene structure having a capacitor trench and an interconnect trench, forming a first electrode a dielectric of the capacitor, and, depositing a metal within said capacitor trench and said interconnection trench wherein the metal forms a second electrode of the capacitor and also forms an interconnection between layers of an interconnecting structure of a semiconductor device. A semiconductor structure, comprising a dual damascene structure having a capacitor trench for a capacitor, the capacitor including a first electrode, a second electrode, and a high-K dielectric between the first and second electrodes, the high-k dielectric configured to seal the first electrode from the second electrode and from subsequent wiring layers of the interconnecting structure of the semiconductor device, and, an interconnection trench for a metal interconnection to form an interconnection between the interconnecting structure of the semiconductor device.

Description

FIELD OF THE INVENTION[0001]The present invention relates generally to semiconductor devices and methods of fabricating semiconductor devices, and, more particularly, to a metal-insulator-metal (MIM) capacitor and a method for integrating a MIM capacitor in back end of line (BEOL) wiring levels of a semiconductor integrated circuit (IC).BACKGROUND OF THE INVENTION[0002]A MIM capacitor is a component of an IC commonly used in high performance applications in complementary metal-oxide-semiconductor (CMOS) technology. The CMOS technology is used, for example, in microprocessors, microcontrollers, static RAM, and other digital logic circuits.[0003]Typically, the MIM capacitor has a sandwich structure and can be described as a parallel plate capacitor. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating dielectric layer. Both parallel plates are typically formed from Al or AlCu alloys that can be patterned and etched through the use of se...

AI Technical Summary

Benefits of technology

This patent describes a method for making a capacitor structure with electrodes simultaneously formed with interconnection. This method uses a single mask instead of two masks typically required in a fabrication process. The method has advantages such as higher capacitance density, low series resistance, low cost, no alignment mark problem, the same topology at the MIM capacitor area for reliable contact formation, and the possibility to double the capacitor density by vertical stacking of MIM caps.

Problems solved by technology

Thus, the conventional process for integrating the MIM capacitor with the interconnection structure requires a number of depositing steps and etching steps, thereby increasing the production cost and causing the final integrated structure to be complicated.

Subtractive etch, the approach used in fabricating aluminum-based interconnects is inapplicable in the fabrication of copper-based interconnects (or interconnections), due to the lack of volatility of copper-halide complexes at moderate temperatures.

Disadvantages of the self-aligned approach include the need for an etch stop layer (which increases sidewall capacitance), the need for high etch selectivity to the etch stop layer and susceptibility to partial via definition if trench and via are misaligned.

Intervening etch stop layers in via / trench architecture degrade the effective capacitance of the structure and such layers are undesirable.

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