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Method for performing data management in memory device, associated memory device and controller thereof

a memory device and data management technology, applied in the field of flash memory access, can solve the problems of large increase in the error rate of the mlc flash memory, and the instability of the mlc flash memory, and achieve the effect of reducing the error rate and raising the cos

Inactive Publication Date: 2018-07-05
SILICON MOTION INC (TW)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a memory device, method, and controller that can improve performance by managing data access effectively. This reduces errors and does not significantly increase cost.

Problems solved by technology

Improving access control of memories in these portable memory devices remains an issue to be solved in the art.
The MLC flash memory does have instability issues, however.
The error rate of the MLC flash memory may be greatly increased under some circumstances, such that traditional error correction mechanisms are unable to deal with the resultant burst error.

Method used

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  • Method for performing data management in memory device, associated memory device and controller thereof
  • Method for performing data management in memory device, associated memory device and controller thereof
  • Method for performing data management in memory device, associated memory device and controller thereof

Examples

Experimental program
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Embodiment Construction

I. The Memory System

[0019]FIG. 1 is a diagram of a memory device 100 and a host device 200 according to a first embodiment of the present invention. The memory device 100 may be a portable memory device (e.g. a memory card conforming to the SD / MMC, CF, MS or XD specification) or a solid state drive (SSD). In addition, examples of the host device 200 may comprise (but are not limited to): a multifunctional mobile phone, tablet, wearable device, and a personal computer. According to this embodiment, the memory device 100 may comprise a controller and a non-volatile memory, where the non-volatile memory is arranged to store information, the controller is arranged to access the non-volatile memory, and the non-volatile memory may comprise at least one non-volatile memory chip (e.g. one or more non-volatile memory chips). The controller may be a memory controller 110, and the non-volatile memory may be a flash memory 120. The flash memory 120 may comprise at least one flash memory chip (...

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PUM

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Abstract

A method for performing data management in a memory device includes: receiving a set of data from a host device positioned outside the memory device; encoding the set of data according to a first sub-matrix of a predetermined parity-check matrix to generate a partial parity-check code; performing post-processing upon the partial parity-check code according to a predetermined post-processing matrix to generate a parity-check code of the set of data, where the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; and writing / programming a codeword of the set of data into a non-volatile memory of the memory device to allow the memory device to perform error correction when reading the set of data from the non-volatile memory. An associated memory device and a controller thereof are also provided.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The present invention relates to flash memory access, and more particularly, to performing data management in a memory device.2. Description of the Prior Art[0002]Developments in memory technology have led to the wide application of portable memory devices, such as memory cards which conform to the SD / MMC, CF, MS and XD specifications, respectively. Improving access control of memories in these portable memory devices remains an issue to be solved in the art.[0003]NAND flash memories may comprise single level cell (SLC) and multiple level cell (MLC) flash memories. In an SLC flash memory, each transistor used as a memory cell may have any of two electrical charge values, respectively representing the logic values 0 and 1. The storage ability of each transistor used as a memory cell in an MLC flash memory may be fully utilized, where the transistor may be driven by a voltage higher than that in the SLC flash memory, and differ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F11/10H03M13/11
CPCG06F11/1068H03M13/1148G06F11/1048G06F11/1044G06F11/1024G06F11/1016H03M13/616G06F11/1012H03M13/1102H03M13/611
Inventor WANG, YU-LUEN
Owner SILICON MOTION INC (TW)